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首页AM35x ARM微处理器技术参考手册:全面特性与内存映射详解
本文档是关于AM35x ARM微处理器的技术参考手册,由SPRUGR0C文献号标识,发布日期为2009年10月,最新修订于2013年11月。该手册详细介绍了AM35x处理器的关键特性和功能,针对的是Cortex-A8架构。
**1. 引言**
- **概述**: AM35x是一款高度集成的ARM微处理器,集成了多种功能模块,如MPU子系统、片上内存、外部内存接口、DMA控制器、多媒体加速器等。它特别强调了安全特性(仅适用于HS设备)以及全面的电源管理,确保了系统的高效运行和安全性。
- **环境**: 手册考虑了设备的使用环境,可能包括温度、供电条件和兼容的操作系统等,以确保最佳性能。
- **描述与组成部分**:
- **MPU子系统**: 提供处理器核心的功能划分和管理,确保任务调度和权限控制。
- **片上内存**: 包括L3和L4存储区域,用于存储操作系统内核、缓存数据和部分硬件控制信息。
- **外部内存接口**: 支持与不同类型存储设备的通信,如SDRAM、NAND闪存等。
- **DMA控制器**: 提供高速数据传输,减轻CPU在数据处理上的负担。
- **多媒体加速器**: 专为图形处理、视频编码解码等任务设计,提升多媒体性能。
- **安全特性**: 对于HS设备,手册强调了加密和安全措施,保护敏感数据和操作。
- **电源管理与外围设备**: 优化功耗管理和各种外设接口,如USB、UART等。
**2. 内存映射**
- **全局内存空间映射**: 明确了处理器内部不同层级的内存分布,便于理解和编程。
- **L3和L4内存空间**: L3主要存放高速缓存,L4则进一步细分为核心内存、唤醒内存、外围设备内存和仿真内存。
- **访问限制**: 注重对寄存器的访问规则,以确保正确和安全的硬件操作。
- **IPSS内存空间映射**: IPSS( Intellectual Property Subsystem)可能包含专用硬件加速器或定制逻辑,有自己的独立内存空间。
这份技术参考手册为开发者提供了深入理解AM35x ARM微处理器的架构、内存管理以及如何利用其各种特性进行高效开发的全面指南。对于任何从事ARM平台软件开发或硬件设计的人来说,这是不可或缺的参考资料。通过阅读和理解这些内容,工程师可以优化系统性能,减少中断处理时间,并确保代码在复杂环境下稳定运行。
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7.3.1 External SDMA Request Interface Description ............................................................. 796
7.3.2 Clocking, Reset, and Power-Management Scheme ........................................................ 797
7.3.2.1 Clocking .................................................................................................... 797
7.3.2.2 Resets ...................................................................................................... 798
7.3.2.2.1 Asynchronous Hardware Reset .................................................................... 798
7.3.2.2.2 Software Reset Through the Configuration Port ................................................. 798
7.3.2.3 Power Domain ............................................................................................ 798
7.3.3 Hardware Requests ............................................................................................. 798
7.3.3.1 Interrupts to the MPU Subsystem ...................................................................... 798
7.3.3.2 DMA Requests to the SDMA Controller ............................................................... 799
7.4 SDMA Functional Description .......................................................................................... 802
7.4.1 Logical Channel Transfer Overview .......................................................................... 802
7.4.2 FIFO Queue Memory Pool ..................................................................................... 804
7.4.3 Addressing Modes .............................................................................................. 804
7.4.4 Packed Accesses ............................................................................................... 808
7.4.5 Burst Transactions .............................................................................................. 809
7.4.6 Endianism Conversion ......................................................................................... 809
7.4.7 Transfer Synchronization ...................................................................................... 809
7.4.7.1 Software Synchronization ................................................................................ 809
7.4.7.2 Hardware Synchronization .............................................................................. 809
7.4.8 Thread Budget Allocation ...................................................................................... 812
7.4.9 FIFO Budget Allocation ........................................................................................ 812
7.4.10 Chained Logical Channel Transfers ......................................................................... 813
7.4.11 Reprogramming an Active Channel ......................................................................... 813
7.4.12 Interrupt Generation ........................................................................................... 814
7.4.13 Packet Synchronization ....................................................................................... 814
7.4.14 Graphics Acceleration Support ............................................................................... 815
7.4.15 Supervisor Modes .............................................................................................. 816
7.4.16 Posted and Nonposted Writes ............................................................................... 816
7.4.17 Disabling a Channel During Transfer ........................................................................ 816
7.4.18 FIFO Draining Mechanism .................................................................................... 816
7.4.19 Reset ............................................................................................................ 817
7.4.20 Power Management ........................................................................................... 817
7.4.20.1 Interconnect Clock Auto-Idle ............................................................................ 817
7.4.20.2 Automatic Standby Mode ................................................................................ 817
7.5 SDMA Basic Programming Model ..................................................................................... 818
7.5.1 Setup Configuration ............................................................................................. 818
7.5.2 Software-Triggered (Nonsynchronized) Transfer ........................................................... 818
7.5.3 Hardware-Synchronized Transfer ............................................................................. 820
7.5.4 Synchronized Transfer Monitoring Using CDAC ............................................................ 822
7.5.5 Concurrent Software and Hardware Synchronization ...................................................... 822
7.5.6 Chained Transfer ................................................................................................ 823
7.5.7 90-Degree Clockwise Image Rotation ........................................................................ 823
7.5.8 Graphic Operations ............................................................................................. 824
7.6 SDMA Use Cases and Tips ............................................................................................ 824
7.6.1 Camcorder Use Case: How to Configure SDMA to Handle Transfers With McBSP2 and MMC to
External DRAM .................................................................................................. 824
7.6.1.1 Introduction ................................................................................................ 825
7.6.1.2 SDMA Configuration to Transfer Data Between the McBSP and External DRAM ............... 825
7.6.1.2.1 Overview .............................................................................................. 825
7.6.1.2.2 Environment ........................................................................................... 825
7.6.1.2.3 Data Path .............................................................................................. 825
7.6.1.2.4 Programming Flow ................................................................................... 826
7.6.1.3 SDMA Configuration to Transfer Data Between MMC and External DRAM ...................... 828
16
Contents SPRUGR0C–October 2009–Revised November 2013
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7.6.1.3.1 Overview .............................................................................................. 828
7.6.1.3.2 Programming Flow ................................................................................... 829
7.7 SDMA Registers Manual ................................................................................................ 832
7.7.1 SDMA Instance Summary ..................................................................................... 832
7.7.2 SDMA Register Summary ..................................................................................... 832
7.7.3 SDMA Register Description .................................................................................... 833
8 Interrupt Controller (INTC) ................................................................................................ 858
8.1 Interrupt Controller Overview ........................................................................................... 859
8.2 Interrupt Controller Environment ....................................................................................... 860
8.3 MPU Subsystem INTCPS Integration ................................................................................. 861
8.3.1 Clocking, Reset, and Power Management Scheme ........................................................ 861
8.3.1.1 MPU Subsystem INTC Clocks .......................................................................... 861
8.3.1.2 Hardware and Software Reset .......................................................................... 861
8.3.1.3 Power Management ...................................................................................... 862
8.3.2 Interrupt Request Lines ........................................................................................ 862
8.4 Interrupt Controller Functional Description ........................................................................... 864
8.4.1 Interrupt Processing ............................................................................................ 867
8.4.1.1 Input Selection ............................................................................................ 867
8.4.1.2 Masking .................................................................................................... 867
8.4.1.2.1 Individual Masking ................................................................................... 867
8.4.1.2.2 Global Masking (HS Devices Only) ................................................................ 867
8.4.1.2.3 Priority Masking ...................................................................................... 867
8.4.1.3 Priority Sorting ............................................................................................ 867
8.4.2 Secure Interrupts (HS Devices Only) ......................................................................... 868
8.4.3 Register Protection ............................................................................................. 868
8.4.4 Module Power Saving .......................................................................................... 868
8.4.5 Interrupt Latency ................................................................................................ 868
8.5 Interrupt Basic Programming Model ................................................................................... 869
8.5.1 Initialization Sequence ......................................................................................... 869
8.5.2 MPU INTC Processing Sequence ............................................................................ 869
8.5.3 MPU INTC Preemptive Processing Sequence .............................................................. 873
8.5.4 MPU INTC Spurious Interrupt Handling ...................................................................... 876
8.6 Interrupt Controller Registers ........................................................................................... 877
8.6.1 Register Mapping Summary ................................................................................... 877
8.6.2 MPU INTC Register Descriptions ............................................................................. 879
8.6.2.1 INTCPS_SYSCONFIG ................................................................................... 879
8.6.2.2 INTCPS_SYSSTATUS ................................................................................... 879
8.6.2.3 INTCPS_SIR_IRQ ........................................................................................ 880
8.6.2.4 INTCPS_SIR_FIQ ........................................................................................ 880
8.6.2.5 INTCPS_CONTROL ...................................................................................... 881
8.6.2.6 INTCPS_PROTECTION ................................................................................. 881
8.6.2.7 INTCPS_IDLE ............................................................................................. 882
8.6.2.8 INTCPS_IRQ_PRIORITY ................................................................................ 882
8.6.2.9 INTCPS_FIQ_PRIORITY ................................................................................ 883
8.6.2.10 INTCPS_THRESHOLD .................................................................................. 883
8.6.2.11 INTCPS_ITRn ............................................................................................. 883
8.6.2.12 INTCPS_MIRn ............................................................................................ 884
8.6.2.13 INTCPS_MIR_CLEARn .................................................................................. 884
8.6.2.14 INTCPS_MIR_SETn ...................................................................................... 885
8.6.2.15 INTCPS_ISR_SETn ...................................................................................... 885
8.6.2.16 INTCPS_ISR_CLEARn .................................................................................. 886
8.6.2.17 INTCPS_PENDING_IRQn ............................................................................... 886
8.6.2.18 INTCPS_PENDING_FIQn ............................................................................... 887
17
SPRUGR0C–October 2009–Revised November 2013 Contents
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8.6.2.19 INTCPS_ILRm ............................................................................................ 887
8.6.3 Device INTC Initialization Register Descriptions ............................................................ 888
8.6.3.1 INTC_INIT_REGISTER1 ................................................................................ 888
8.6.3.2 INTC_INIT_REGISTER2 ................................................................................ 888
9 Memory Subsystem ......................................................................................................... 889
9.1 General-Purpose Memory Controller (GPMC) ....................................................................... 890
9.1.1 General-Purpose Memory Controller Overview ............................................................. 890
9.1.1.1 GPMC Features ........................................................................................... 891
9.1.2 GPMC Environment ............................................................................................ 892
9.1.3 GPMC Integration ............................................................................................... 895
9.1.3.1 Description ................................................................................................. 895
9.1.3.2 Clocking, Reset, and Power Management Scheme ................................................. 896
9.1.3.2.1 Clocking ............................................................................................... 896
9.1.3.2.2 Hardware Reset ...................................................................................... 896
9.1.3.2.3 Software Reset ....................................................................................... 896
9.1.3.2.4 Power Domain, Power Saving, and Reset Management ....................................... 896
9.1.3.2.5 Hardware Requests .................................................................................. 896
9.1.3.3 GPMC Address and Data Bus .......................................................................... 897
9.1.3.3.1 GPMC I/O Configuration Setting (In Default Pinout Mode 0) ................................... 897
9.1.3.3.2 GPMC CS0 Default Configuration at IC Reset ................................................... 898
9.1.4 GPMC Functional Description ................................................................................. 899
9.1.4.1 Description ................................................................................................. 899
9.1.4.2 L3 Interconnect Interface ................................................................................ 900
9.1.4.3 Address Decoder, GPMC Configuration, and Chip-Select Configuration Register File ......... 900
9.1.4.4 Error Correction Code Engine (ECC) .................................................................. 901
9.1.4.5 Prefetch and Write-Posting Engine ..................................................................... 901
9.1.4.6 External Device/Memory Port Interface ................................................................ 901
9.1.5 GPMC Basic Programming Model ............................................................................ 902
9.1.5.1 Chip-Select Base Address and Region Size Configuration ......................................... 902
9.1.5.2 Access Protocol Configuration .......................................................................... 903
9.1.5.2.1 Supported Devices ................................................................................... 903
9.1.5.2.2 Access Size Adaptation and Device Width ....................................................... 904
9.1.5.2.3 Address/Data-Multiplexing Interface ............................................................... 904
9.1.5.2.4 Address and Data Bus ............................................................................... 904
9.1.5.2.5 Asynchronous and Synchronous Access ......................................................... 904
9.1.5.2.6 Page and Burst Support ............................................................................. 905
9.1.5.2.7 System Burst Versus External Device Burst Support ........................................... 905
9.1.5.3 Timing Setting ............................................................................................. 906
9.1.5.3.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME) .............. 907
9.1.5.3.2 nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /
CSWROFFTIME / CSEXTRADELAY) ............................................................. 907
9.1.5.3.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY) .............. 908
9.1.5.3.4 nOE/nRE: Output Enable / Read Enable Signal Control Assertion / Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY) ............................................... 908
9.1.5.3.5 nWE: Write Enable Signal Control Assertion / Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY) ................................................................................... 908
9.1.5.3.6 GPMC_CLK ........................................................................................... 909
9.1.5.3.7 GPMC_CLK and Control Signals Setup and Hold ............................................... 909
9.1.5.3.8 Access Time (RDACCESSTIME / WRACCESSTIME) .......................................... 910
9.1.5.3.9 Page Burst Access Time (PAGEBURSTACCESSTIME) ....................................... 910
9.1.5.3.10 Bus Keeping Support ................................................................................ 911
9.1.5.4 WAIT Pin Monitoring Control ............................................................................ 911
9.1.5.4.1 Wait Monitoring During an Asynchronous Read Access ........................................ 912
18
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9.1.5.4.2 Wait Monitoring During an Asynchronous Write Access ........................................ 913
9.1.5.4.3 Wait Monitoring During a Synchronous Read Access .......................................... 914
9.1.5.4.4 Wait Monitoring During a Synchronous Write Access ........................................... 915
9.1.5.4.5 WAIT with NAND Device ............................................................................ 916
9.1.5.4.6 Idle Cycle Control between Successive Accesses .............................................. 916
9.1.5.4.7 Slow Device Support (TIMEPARAGRANULARITY Parameter) ................................ 918
9.1.5.5 gpmc_io_dir Pin ........................................................................................... 918
9.1.5.6 Reset ....................................................................................................... 918
9.1.5.7 Write Protect (nWP) ...................................................................................... 919
9.1.5.8 Byte Enable (nBE1/nBE0) ............................................................................... 919
9.1.5.9 Asynchronous Access Description ..................................................................... 920
9.1.5.9.1 Asynchronous Single Read ......................................................................... 920
9.1.5.9.2 Asynchronous Single Write ......................................................................... 922
9.1.5.9.3 Asynchronous Multiple (Page Mode) Read ....................................................... 924
9.1.5.10 Synchronous Access ..................................................................................... 926
9.1.5.10.1 Synchronous Single Read .......................................................................... 926
9.1.5.10.2 Synchronous Single Write .......................................................................... 928
9.1.5.10.3 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst with Wraparound Capability)
.......................................................................................................... 929
9.1.5.10.4 Synchronous Multiple (Burst) Write ................................................................ 931
9.1.5.11 pSRAM Basic Programming Model .................................................................... 933
9.1.5.12 Error Handling ............................................................................................. 934
9.1.5.13 Boot Configuration ........................................................................................ 934
9.1.5.14 NAND Device Basic Programming Model ............................................................. 934
9.1.5.14.1 NAND Memory Device in Byte or Word16 Stream Mode ....................................... 934
9.1.5.14.2 NAND Device-Ready Pin ........................................................................... 941
9.1.5.14.3 ECC Calculator ....................................................................................... 942
9.1.5.14.4 Prefetch and Write-Posting Engine ................................................................ 958
9.1.6 GPMC Use Cases and Tips ................................................................................... 966
9.1.6.1 How to Set GPMC Timing Parameters for Typical Accesses ....................................... 966
9.1.6.1.1 External Memory Attached to the GPMC Module ................................................ 966
9.1.6.1.2 Typical GPMC Setup ................................................................................ 966
9.1.6.2 How to Choose a Suitable Memory to use with the GPMC ......................................... 972
9.1.6.2.1 Supported Memories or Devices ................................................................... 972
9.1.6.2.2 GPMC Features and Settings ...................................................................... 974
9.1.7 GPMC Registers ................................................................................................ 975
9.1.7.1 GPMC Register Mapping Summary .................................................................... 975
9.1.7.2 GPMC Register Descriptions ............................................................................ 977
9.1.7.2.1 GPMC_SYSCONFIG ................................................................................ 977
9.1.7.2.2 GPMC_SYSSTATUS ................................................................................ 978
9.1.7.2.3 GPMC_IRQSTATUS ................................................................................. 979
9.1.7.2.4 GPMC_IRQENABLE ................................................................................. 981
9.1.7.2.5 GPMC_TIMEOUT_CONTROL ..................................................................... 982
9.1.7.2.6 GPMC_ERR_ADDRESS ............................................................................ 983
9.1.7.2.7 GPMC_ERR_TYPE .................................................................................. 984
9.1.7.2.8 GPMC_CONFIG ...................................................................................... 985
9.1.7.2.9 GPMC_STATUS ..................................................................................... 986
9.1.7.2.10 GPMC_CONFIG1_i .................................................................................. 987
9.1.7.2.11 GPMC_CONFIG2_i .................................................................................. 990
9.1.7.2.12 GPMC_CONFIG3_i .................................................................................. 991
9.1.7.2.13 GPMC_CONFIG4_i .................................................................................. 992
9.1.7.2.14 GPMC_CONFIG5_i .................................................................................. 993
9.1.7.2.15 GPMC_CONFIG6_i .................................................................................. 994
9.1.7.2.16 GPMC_CONFIG7_i .................................................................................. 995
19
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9.1.7.2.17 GPMC_NAND_COMMAND_i ...................................................................... 996
9.1.7.2.18 GPMC_NAND_ADDRESS_i ........................................................................ 997
9.1.7.2.19 GPMC_NAND_DATA_i ............................................................................. 997
9.1.7.2.20 GPMC_PREFETCH_CONFIG1 .................................................................... 998
9.1.7.2.21 GPMC_PREFETCH_CONFIG2 .................................................................. 1000
9.1.7.2.22 GPMC_PREFETCH_CONTROL ................................................................. 1000
9.1.7.2.23 GPMC_PREFETCH_STATUS .................................................................... 1001
9.1.7.2.24 GPMC_ECC_CONFIG ............................................................................. 1002
9.1.7.2.25 GPMC_ECC_CONTROL .......................................................................... 1003
9.1.7.2.26 GPMC_ECC_SIZE_CONFIG ..................................................................... 1004
9.1.7.2.27 GPMC_ECCj_RESULT ............................................................................ 1006
9.1.7.2.28 GPMC_BCH_RESULT0_i ......................................................................... 1007
9.1.7.2.29 GPMC_BCH_RESULT1_i ......................................................................... 1007
9.1.7.2.30 GPMC_BCH_RESULT2_i ......................................................................... 1007
9.1.7.2.31 GPMC_BCH_RESULT3_i ......................................................................... 1008
9.1.7.2.32 GPMC_BCH_SWDATA ............................................................................ 1008
9.2 SDRAM Controller (SDRC) Subsystem ............................................................................. 1009
9.2.1 SDRC Subsystem Overview ................................................................................. 1009
9.2.1.1 Features .................................................................................................. 1010
9.2.2 SDRC Subsystem Integration ................................................................................ 1011
9.2.2.1 Clocking, Reset, and Power Management Scheme ................................................ 1012
9.2.2.1.1 Clocking .............................................................................................. 1012
9.2.2.1.2 Hardware Reset ..................................................................................... 1012
9.2.2.1.3 Software Reset ...................................................................................... 1012
9.2.3 SDRC Subsystem Functional Description .................................................................. 1013
9.2.3.1 SDRAM Memory Scheduler ........................................................................... 1013
9.2.3.1.1 Memory Access Scheduling ....................................................................... 1014
9.2.3.1.2 Arbitration Policy .................................................................................... 1014
9.2.3.1.3 Internal Class Arbitration ........................................................................... 1016
9.2.3.1.4 Security Firewall .................................................................................... 1017
9.2.3.1.5 Rotation Engine ..................................................................................... 1020
9.2.3.1.6 Register Security .................................................................................... 1021
9.2.3.1.7 Security Violation Reporting ....................................................................... 1022
9.2.3.2 Module Power Saving .................................................................................. 1022
9.2.3.3 System Power Management ........................................................................... 1022
9.2.3.4 External Memory Interface Module (EMIF) .......................................................... 1023
9.2.3.4.1 EMIF Overview ...................................................................................... 1023
9.2.3.4.2 Functional Description ............................................................................. 1025
9.2.3.4.3 EMIF Registers ...................................................................................... 1040
9.2.3.4.4 Interrupt Conditions ................................................................................. 1069
9.2.3.4.5 Power Management ................................................................................ 1069
9.2.3.4.6 Programming/Usage Guide ....................................................................... 1075
9.2.4 SMS Basic Programming Model ............................................................................. 1075
9.2.4.1 SMS Firewall Usage .................................................................................... 1075
9.2.4.2 VRFB Context Configuration ........................................................................... 1076
9.2.4.3 Memory-Access Scheduler Configuration ............................................................ 1078
9.2.4.4 Error Logging ............................................................................................ 1078
9.2.5 SDRC Use Cases and Tips .................................................................................. 1079
9.2.5.1 How to Program the VRFB ............................................................................ 1079
9.2.5.1.1 VRFB Rotation Mechanism ........................................................................ 1079
9.2.5.1.2 Setting a VRFB Context ........................................................................... 1081
9.2.5.1.3 Applicative Use Case and Tips ................................................................... 1084
9.2.5.2 SMS Mode of Operation ................................................................................ 1087
20
Contents SPRUGR0C–October 2009–Revised November 2013
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