DDR5 SPD规格：JEDEC JESD400-5详解

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"JEDEC JESD400-5标准详细定义了DDR5内存模块的串行存在检测（SPD）内容。该文档旨在提供关于内存通道上所有模块的关键信息，供系统的BIOS用于正确初始化和优化系统内存。DDR5 SPD非易失性存储器的容量在标准中有所规定。" DDR5 Serial Presence Detect (SPD) 是DDR5内存技术中的一个重要组成部分，它是一种存储关键信息的小型非易失性存储器，位于内存模块上。JEDEC（Joint Electron Device Engineering Council，联合电子设备工程委员会）是制定半导体行业标准的组织，JESD400-5是JEDEC发布的关于DDR5 SPD的规范。在DDR5内存系统中，SPD数据包含了关于内存模块的多个方面信息，如内存的类型、速度、电压等级、时序设置、散热信息、制造商信息等。这些数据对于系统BIOS来说至关重要，因为它们需要这些信息来识别并配置内存条，确保系统的稳定运行和性能优化。与DDR4相比，DDR5 SPD引入了更多的特性以支持更高的内存带宽、更低的功耗和更先进的功能。 DDR5 SPD的一个显著改进是其容量的增加。由于DDR5内存模块的技术升级，SPD需要存储更多数据以适应新的特性和功能，比如动态电压和频率调整（DVFS）、电源管理设置、多列数据包处理（Multi-Rank Interleaving）等。这使得DDR5 SPD能够支持更复杂的系统配置和未来扩展。此外，DDR5 SPD还引入了更快速的通信协议，使用了更高速的I2C接口，以满足更快的数据传输需求。这个接口允许系统更快地读取SPD信息，从而加快系统的启动时间和配置过程。 JEDEC标准的制定遵循严格的程序，包括董事局级别的审查和法律顾问的确认。这些标准的目的是为了消除制造商和购买者之间的误解，促进产品的互换性和改进，帮助购买者迅速选择并获取合适的内存产品，无论是在国内还是国际市场。需要注意的是，JEDEC标准的制定不考虑是否涉及专利，也不承担任何专利所有者的责任，或对采用JEDEC标准的各方有任何义务。这意味着标准的使用者需要自行解决可能存在的知识产权问题。 JESD400-5 DDR5 SPD标准详细定义了内存模块的配置信息，为系统提供了自动识别和优化内存性能的依据，同时也反映了DDR5技术在性能、效率和扩展性方面的进步。

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JEDEC Standard No. 400-5

Page 6

4.6 NVDIMM-N Overlay Schema

Key Byte 2 contains value 0x12 (DDR5)

Key Byte 3 contains any of the following values:

• 0x9X, NVDIMM-N Hybrid

where X refers to the base memory architecture

4.7 NVDIMM-P Overlay Schema

Key Byte 2 contains value 0x12 (DDR5)

Key Byte 3 contains any of the following values:

• 0xAX, NVDIMM-P Hybrid

where X refers to the base memory architecture

After programming the SPD contents, suppliers of JEDEC compliant modules must set the write protect bits for SPD

device blocks 0 through 7. See JESD300-5 SPD5118 Device Specification for details on the Write Protect command

protocol.

Block Range Description

0 0~63 0x000~0x03F Base Configuration and DRAM Parameters

1 64~127 0x040~0x07F Base Configuration and DRAM Parameters

2 128~191 0x080~0x0BF ...

192~239 0x0C0~0x0EF Insert Annex A.0: Common

240~255 0x0D0~0x0FF Insert Annex A.6: NVDIMM-N Memory Module Types

4 256~319 0x100~0x13F Insert Annex A.6: NVDIMM-N Memory Module Types

5 320~383 0x140~0x17F Insert Annex A.6: NVDIMM-N Memory Module Types

6 384~447 0x180~0x1BF Insert Annex A.6: NVDIMM-N Memory Module Types

7~15 448~1023 0x180~0x3FF ...

Block Range Description

0 0~63 0x000~0x03F Base Configuration and DRAM Parameters

1 64~127 0x040~0x07F Base Configuration and DRAM Parameters

2 128~191 0x080~0x0BF ...

192~239 0x0C0~0x0EF Insert Annex A.0: Common

240~255 0x0D0~0x0FF Insert Annex A.7: NVDIMM-P Memory Module Types

4 256~319 0x100~0x13F Insert Annex A.7: NVDIMM-P Memory Module Types

5 320~383 0x140~0x17F Insert Annex A.7: NVDIMM-P Memory Module Types

6 384~447 0x180~0x1BF Insert Annex A.7: NVDIMM-P Memory Module Types

7~15 448~1023 0x180~0x3FF ...

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JEDEC

JEDEC Standard No. 400-5

Page 7

5 Parsing the SPD

The system BIOS will acquire information from the SPD in order to properly configure the system’s memory

controller. It is assumed the BIOS will parse the SPD data in the order listed below.

Step 1: Parse Byte 1 - Verify the SPD contents.

The first step is to verify the validity of the contents of the SPD. Calculate and verify that the 16-bit cyclic

redundancy check (CRC) for bytes 0~509 matches the CRC stored in bytes 510~511.

Step 2: Parse Byte 2 - Verify the installed DRAM type is supported.

The first step in parsing the SPD is to verify that the DRAM type installed is supported by looking at DRAM device

type byte 2. While it is usually not possible to physically plug in the wrong memory type, for example a DDR3

module size or key location should prevent insertion into a DDR5 system, there are cases where byte 2 is used to

prevent accidental use of an incompatible memory type.

Step 3: Parse Byte 1 - Verify SPD compatibility. See Section 6 - SPD Revision Progression

The SPD revision byte 1 “encoding” nibble may be used to force legacy systems to reject newer modules. This would

typically only occur if a critical error were found in SPD encoding that would require a “fix”. In this case, as in the

case of an unsupported DRAM type, system initialization must be halted immediately.

The SPD revision stored in Byte 1 applies to all information for the module, including base information and module

specific information. Each SPD revision exactly defines how many bytes are valid in all other SPD blocks. The

number of supported bytes (or bits) may increase from one SPD revision to another within each block as indicated by

the “additions” nibble of the SPD revision. For example, an SPD revision 1.3 has more bytes or bits defined than SPD

revision 1.2.

This progression of SPD contents is important for the BIOS to DIMM compatibility model. An older system may

have a BIOS that only understands SPD revision 1.2 encoding, so if a module is installed that contains revision 1.3

information, the system can accurately interpret all of the historical revision 1.2 information retained in the module

that is the subset of the revision 1.3 specification. Similarly, if a module with SPD revision 1.1 information is

installed, that same BIOS can interpret all information that was current at the time that SPD 1.1 was defined.

Therefore, BIOSes must maintain a knowledge of the active information for each historical SPD revision in order to

support older modules.

Some Relevant SPD Bytes for Parsing

SPD Byte(s) Definition

1 SPD revision for the base section of the SPD

2 DRAM interface type presented or emulated

3 Memory module interface type

0~125 Base configuration and DRAM parameters

192 SPD revision for the module specific annex

192~239 Common module parameters

240~445 Module specific parameters

510~511 CRC for bytes 0~509

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JEDEC

JEDEC Standard No. 400-5

Page 8

5 Parsing the SPD (cont’d)

New in DDR5 SPD contents definition is a separate revision byte for sections of the contents. For example, the

revision byte 1 covers only the base configuration information blocks, bytes 0 to 127. There is a separate revision

byte for other sections such as the standard module parameters in bytes 192-447. The same scheme of contents and

additions nibbles is used in each of these sections to allow forward and backward compatibility. Having separate

revision levels in various sections of the SPD contents allows those sections to change independently.

Step 4: Parse Byte 3 - Determine module type and appropriate overlays.

Key byte 3 for module type determines the subsequent use of overlay information. Byte 3 defines the host to module

interface style: unbuffered, registered, load reduced, differential, or hybrid. Standard module types are defined in

Annexes A.x.

Step 5: Parse Bytes 0~127 - Make base configuration settings to memory interface based on these bytes.

All module types are required to read and interpret this block of data to set up the DRAM type, maximum operating

frequency, the number of row, column, bank bits, write recovery time, etc. While these bytes primarily describe the

timing of the DRAMs, timing represents the capabilities of the module and it may be necessary to downgrade the

timing based on other factors including layout or support components on the module, such as registers.

Step 6: Parse Byte 192 - Module-specific annex SPD revision.

This byte determines the encoding level and additions level of the module specific bytes of the SPD. Separating the

base section of the SPD and module specific section prevents unnecessary churn; for example, if the UDIMM annex

changes, the SPD for RDIMM/LRDIMM module need not change.

Step 7: Parse Bytes 193~447 - Configure standard module memory interface.

These bytes will be referenced and used by the system as needed based on the Standard module type that was

determined after Byte 3 was parsed as indicated in Step 2. Bytes 192~239 are common byte definitions for all module

types as defined in Annex A.0. Bytes 240~447 are coded differently for each standard module type as defined in

Annex A.x.

6 SPD Revision Progression

SPD Contents sections have a revision code for that section of the specification. This allows each section to evolve

over time independently as much as possible. For example a system may need to parse one revision level for the Base

Configuration section (bytes 0~127) and a different revision level for the Standard Module Parameters section (bytes

192-447).

The Additions Level is never reduced even after an increment of the Encoding Level. For example, if the current SPD

revision level were 1.2 and a change in Encoding Level were approved, the next revision level would be 2.2. If

additions to revision 2.2 were approved, the next revision would be 2.3. Changes in the Encoding Level are extremely

rare, however, since they can create incompatibilities with older systems.

The exceptions to the above rule are the SPD revision levels used during development prior to the

Revision 1.0 release. Revisions 0.0 through 0.9 are used to indicate sequential pre-production SPD revision levels,

however the first production release will be Revision 1.0.

Hypothetical SPD Revision Progression Showing Revision Relationships

Section

Bytes

Revision Byte

Base Configuration and SDRAM Parameters 0~127 1

Standard Module Parameters 192~447 192

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JEDEC

JEDEC Standard No. 400-5

Page 9

6 SPD Revision Progression (cont’d)

A hypothetical progression is shown to illustrate the relationship between feature updates, typographical error

corrections, specification revisions, and dates. In order to reduce the number of module requalifications, policy is to

issue SPD releases once per year, typically in June (publication to the JEDEC public site typically takes an additional

3 months from committee approval).

7 Address Map

The following is the SPD address map for all DDR5 modules. It describes where the individual lookup table entries

will be held in the serial non-volatile memory. Consistent with the definition of DDR5 generation SPD devices which

have 16 individual write protection blocks of 64 bytes in length each, the SPD contents are aligned with these blocks

as follows:

After programming the SPD contents, suppliers of JEDEC compliant modules must set the write protect bits for SPD

device blocks 0 through 7. See the SPD5xx8 Device Specification for details on the block protect command protocol.

SPD Byte 1 SPD Byte 192

Year Description Document Release Date Base Solder Down UDIMM RDIMM/LRDIMM DDIMM NVDIMM-N NVDIMM-P

0 Initial SPD document release JESD400-5 June 2021 1.0 1.0 1.0 1.0 1.0 0.1 0.1

0 Typographical fixes JESD400-5 September 2021 1.0 1.0 1.0 1.0 1.0 0.1 0.1

0 Typographical fixes JESD400-5 December 2021 1.0 1.0 1.0 1.0 1.0 0.1 0.1

Additions to base, RDIMM

First release NVDIMM-P

Pre-production additions to NVDIMM-N

JESD400-5A June 2022 1.1 1.0 1.0 1.1 1.0 0.2 1.0

1 Typographical fixes JESD400-5A September 2022 1.1 1.0 1.0 1.1 1.0 0.2 1.0

1 Typographical fixes JESD400-5A March 2023 1.1 1.0 1.0 1.1 1.0 0.2 1.0

Additions to base, RDIMM, DDIMM

Additions to NVDIMM-P

First release NVDIMM-N

JESD400-5B June 2023 1.2 1.0 1.0 1.2 1.1 1.0 1.1

3 Additions to base JESD400-5C June 2024 1.3 1.0 1.0 1.2 1.1 1.0 1.1

3 Typographical fixes JESD400-5C March 2025 1.3 1.0 1.0 1.2 1.1 1.0 1.1

4 Additions to base, NVDIMM-N JESD400-5D June 2025 1.4 1.0 1.0 1.2 1.1 1.1 1.1

Block Range Description

0 0~63 0x000~0x03F Base Configuration and DRAM Parameters

1 64~127 0x040~0x07F Base Configuration and DRAM Parameters

2 128~191 0x080~0x0BF Reserved for future use

192~239 0x0C0~0x0EF Common Module Parameters -- See Annex A.0 for details

240~255 0x0D0~0x0FF Standard Module Parameters -- See annexes A.x for details

4 256~319 0x100~0x13F Standard Module Parameters -- See annexes A.x for details

5 320~383 0x140~0x17F Standard Module Parameters -- See annexes A.x for details

6 384~447 0x180~0x1BF Standard Module Parameters -- See annexes A.x for details

448~509 0x1C0~0x1FD Reserved for future use

510~511 0x1FE~0x1FF CRC for bytes 0~509

8 512~575 0x200~0x23F Manufacturing Information

9 576~639 0x240~0x27F Manufacturing Information

10 640~703 0x280~0x2BF

End User Programmable

11 704~767 0x2C0~0x2FF End User Programmable

12 768~831 0x300~0x33F End User Programmable

13 832~895 0x340~0x37F End User Programmable

14 896~959 0x380~0x3BF End User Programmable

15 960~1023 0x3C0~0x3FF End User Programmable

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JEDEC

JEDEC Standard No. 400-5

Page 10

7 Address Map (cont’d)

7.1 Blocks 0~1: Base Configuration and DRAM Parameters

Table 1 details the location of each byte in this block.

Table 1 — Blocks 0~1: Base Configuration and DRAM Parameters

Byte Number

Function Described

Notes

0 0x000 Number of Bytes in SPD Device and Beta Level

1 0x001 SPD Revision for Base Configuration Parameters

2 0x002 Key Byte / Host Bus Command Protocol Type

3 0x003 Key Byte / Module Type

4 0x004 First SDRAM Density and Package 1

5 0x005 First SDRAM Addressing 1

6 0x006 First SDRAM I/O Width 1

7 0x007 First SDRAM Bank Groups and Banks Per Bank Group 1

8 0x008 Second SDRAM Density and Package 1

9 0x009 Second SDRAM Addressing 1

10 0x00A Second SDRAM I/O Width 1

11 0x00B Second SDRAM Bank Groups and Banks Per Bank Group 1

12 0x00C SDRAM BL32 and Post Package Repair 1

13 0x00D SDRAM Duty Cycle Adjuster and Partial Array Self Refresh 1

14 0x00E SDRAM Fault Handling 1

15 0x00F Reserved

16 0x010 SDRAM Nominal Voltage, VDD 1

17 0x011 SDRAM Nominal Voltage, VDDQ 1

18 0x012 SDRAM Nominal Voltage, VPP 1

19 0x013 SDRAM Timing 1

20 0x014

SDRAM Minimum Cycle Time (t

CKAVG

min), Least Significant Byte

21 0x015

SDRAM Minimum Cycle Time (t

CKAVG

min), Most Significant Byte

22 0x016

SDRAM Maximum Cycle Time (t

CKAVG

max), Least Significant Byte

23 0x017

SDRAM Maximum Cycle Time (t

CKAVG

max), Most Significant Byte

24 0x018 CAS Latencies Supported, First Byte 1

25 0x019 CAS Latencies Supported, Second Byte 1

26 0x01A CAS Latencies Supported, Third Byte 1

27 0x01B CAS Latencies Supported, Fourth Byte 1

28 0x01C CAS Latencies Supported, Fifth Byte 1

29 0x01D Reserved 1

30 0x01E

SDRAM Minimum CAS Latency Time (t

min), Least Significant Byte

31 0x01F

SDRAM Minimum CAS Latency Time (t

min), Most Significant Byte

32 0x020

SDRAM Minimum RAS to CAS Delay Time (t

RCD

min), Least Significant Byte

33 0x021

SDRAM Minimum RAS to CAS Delay Time (t

RCD

min), Most Significant Byte

NOTE 1 From DDR5 SDRAM datasheet.

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