ACMIS Rev.0.95a
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DSFP MSA Copyright 2018 Page 13 of 74
acknowledged by the slave for all bytes. Read data operations shall be acknowledged by 1
the master for all but the final byte read, for which the master shall respond with a non-2
acknowledge (NACK) by permitting SDA to remain high and followed by a STOP. 3
2.4.1.4 Clock Stretching 4
To extend the transfer the slave asserts clock low. This should be initiated while the clock is 5
low. This can be used by the slave to delay completion of the operation. 6
2.4.2 Reset TWI 7
2.4.2.1 Power On Reset 8
The interface shall enter a reset state upon Application of power. 9
2.4.2.2 TWI Protocol Reset
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Synchronization issues may cause the master and slave to disagree on the specific bit 11
location currently being transferred, the type of operation or even if an operation is in 12
progress. The TWI protocol has no explicitly defined reset mechanism. The following 13
procedure may force completion of the current operation and cause the slave to release 14
SDA. 15
a) The master shall provide up to nine SCL clock cycle (drive low, then high) to the slave 16
b) The master shall monitor SDA while SCL is high on each cycle. 17
c) If the slave releases SDA, it will be high and the master is then free to initiate a START 18
operation for the next transaction 19
d) If SDA remains low after a full nine clock cycles the TWI protocol reset has failed 20
2.4.2.3 Reset Signal
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Some implementations may include a reset signal. If provided, upon assertion of the reset 22
signal the TWI shall transition to the reset state. 23
2.4.3 Format 24
2.4.3.1 Read/Write Controls
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After the start condition, the first 8-bit word of a TWI bus operation shall consist of 26
'1010000' followed by a read/write control bit. 27
The least significant bit indicates if the operation is a data read or write. A read operation is 28
performed if this bit is high and a write operation is executed if this bit is set low. Upon 29
completion of the control word transmission the slave shall assert the SDA signal low to 30
acknowledge delivery (ACK) of the control/address word. 31
2.4.3.2 Address and Data
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Following the read/write control bit, addresses and data words are transmitted in 8-bit 33
words. Data is transferred with the most significant bit (MSB) first. Multiple Byte 34
transactions shall be transmitted in increasing byte address order over the TWI. 35