DSFP_MSA协议详解：两线接口与管理接口规范

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DSFP_MSA协议（Digital Serial Fiber Pair Multi-vendor Specification）是专为光模块设计的一种标准接口规范，由Abridged Common Management Interface Specifications (ACMIS)定义。该协议旨在促进不同厂商之间的光模块管理，确保设备间的兼容性和互操作性。ACMIS共分为六个章节，每个章节都有其特定内容： 1. 概述（Chapter 1）：作为整个文档的开端，这部分会提供DSFP_MSA协议的总体介绍，包括其背景、目标以及它在光模块通信中的重要性。 2. 两线接口（TWI）管理界面（Chapter 2）：这部分是直接源自CMIS Rev.2.91的，详细描述了TWI（Two Wire Interface）的管理接口技术，包括接口的工作原理、时序规范以及信号交互方式。TWI是一种用于串行通信的简化接口，对于数据传输和控制提供了基础架构。 3. 主机与模块的控制与信号理论（Chapter 3）：这一章深入探讨了DSFP_MSA协议中关于如何在主机和光模块之间进行有效通信的理论，包括命令的发送、响应处理以及错误检测机制等。 4. 典型应用与内存映射（Chapter 4）：通过理论的实践应用，展示了如何在实际系统中使用DSFP_MSA协议进行内存访问和管理操作，为开发者提供实际操作指南。 5. 寄存器定义（Chapter 5）：这是协议的核心部分，列出了所有必要的寄存器及其功能，这对于理解和实现DSFP_MSA兼容设备至关重要。 6. 附录（Chapter 6 - 补充资料）：通常包含额外的技术细节、规范更新历史、参考文献列表、图表和表格索引，以及可能的协议变更或补充说明。 DSFP_MSA协议不仅规定了硬件层面的接口细节，还包括了软件开发者的指导，确保了在不同厂商生产的光模块上进行管理操作的统一性和稳定性。遵循这一标准，制造商能够设计出相互兼容的产品，方便用户在多厂商环境下无缝集成和管理光纤设备。通过理解并遵守DSFP_MSA，工程师可以提升系统设计的效率和可靠性。

ACMIS Rev.0.95a

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acknowledged by the slave for all bytes. Read data operations shall be acknowledged by 1

the master for all but the final byte read, for which the master shall respond with a non-2

acknowledge (NACK) by permitting SDA to remain high and followed by a STOP. 3

2.4.1.4 Clock Stretching 4

To extend the transfer the slave asserts clock low. This should be initiated while the clock is 5

low. This can be used by the slave to delay completion of the operation. 6

2.4.2 Reset TWI 7

2.4.2.1 Power On Reset 8

The interface shall enter a reset state upon Application of power. 9

2.4.2.2 TWI Protocol Reset

Synchronization issues may cause the master and slave to disagree on the specific bit 11

location currently being transferred, the type of operation or even if an operation is in 12

progress. The TWI protocol has no explicitly defined reset mechanism. The following 13

procedure may force completion of the current operation and cause the slave to release 14

SDA. 15

a) The master shall provide up to nine SCL clock cycle (drive low, then high) to the slave 16

b) The master shall monitor SDA while SCL is high on each cycle. 17

c) If the slave releases SDA, it will be high and the master is then free to initiate a START 18

operation for the next transaction 19

d) If SDA remains low after a full nine clock cycles the TWI protocol reset has failed 20

2.4.2.3 Reset Signal

Some implementations may include a reset signal. If provided, upon assertion of the reset 22

signal the TWI shall transition to the reset state. 23

2.4.3 Format 24

2.4.3.1 Read/Write Controls

After the start condition, the first 8-bit word of a TWI bus operation shall consist of 26

'1010000' followed by a read/write control bit. 27

The least significant bit indicates if the operation is a data read or write. A read operation is 28

performed if this bit is high and a write operation is executed if this bit is set low. Upon 29

completion of the control word transmission the slave shall assert the SDA signal low to 30

acknowledge delivery (ACK) of the control/address word. 31

2.4.3.2 Address and Data

Following the read/write control bit, addresses and data words are transmitted in 8-bit 33

words. Data is transferred with the most significant bit (MSB) first. Multiple Byte 34

transactions shall be transmitted in increasing byte address order over the TWI. 35

ACMIS Rev.0.95a

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2.5 Read/Write Operations 1

2.5.1 Slave Memory Address Counter (Read and Write Operations) 2

All TWI slaves maintain an internal data word address counter containing the last address 3

accessed during the latest read or write operation, incremented by one. The address 4

counter is incremented whenever a data word is received or sent by the slave. This 5

address remains valid between operations as long as power to the slave is maintained. 6

Upon loss of power to or reset of the module or upon transactions not terminated by a Stop 7

condition, the slave address counter contents may be indeterminate. The address roll-over 8

during read and writes operations is from the last byte of the 128-byte memory page to the 9

first byte of the same page. The host shall use single 2-byte reads to retrieve all 16-bit data, 10

to guarantee data coherency. The module shall prevent the host from acquiring partially 11

updated multi-byte data during a 2-byte read. Clock stretching provides one mechanism to 12

delay the delivery of data until all bytes of one field have been updated. 13

2.5.2 Read Operations 14

2.5.2.1 Current Address Read 15

A current address read operation requires only the slave address read word (10100001) be 16

sent. Once acknowledged by the slave, the current address data word is serially clocked 17

out. The transfer is terminated when the master responds with a NACK and a STOP 18

instead of an acknowledge. 19

Figure 1 Module Current Address Read Operation 20

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2.5.2.2 Random Read 21

A random read operation requires a dummy write operation to load in the target byte 22

address. This is accomplished by the following sequence: The target 8-bit data word 23

address is sent following the device address write word (10100000) and acknowledged by 24

the slave. The master then generates another START condition (aborting the dummy write 25

without incrementing the counter) and a current address read by sending a device read 26

address (10100001). The slave acknowledges the device address and serially clocks out 27

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