?
Data_in Din FIFO_out FIFO
Cnt8_q 8
?
_xbio
_xz
_xod
_xo
_xi
_n
_en
_s
_L _L1
_L
_z
_q
_d
_clk
1. D _L,
_L1 _L2 ..... L lock
2. _s s same
5.1.2
1.
? VHDL
VHDL
?
Cnt8_q STD_LOGIC_VECTOR + Cnt8_q <= Cnt8_q + 1
+ use IEEE .std_logic_arith. all
?
2.
?
?
signal Addr STD_LOGIC_VECTOR(31 downto 0);
alias Top_addr STD_LOGIC_VECTOR(3 downto 0) is Addr(31 downto 28)
3.
Z z
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