3-D片上网络的热感知能源优化：电压频率岛方法

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"这篇研究论文探讨了如何通过在三维(3-D)片上网络(NoC)中引入电压频率岛(VFI)技术来优化热感知能量。针对VFI技术在3-D NoC设计中面临的加剧热问题，以及针对预设计硬平台的优化空间限制，论文提出了一种VFI感知的综合框架，旨在最小化系统能耗并保持3-D NoC平台的热平衡，同时允许设计者自由决定计算组件的映射决策。除了任务调度和计算单元的电压调整外，该框架还考虑了网络流量和热分布的协同优化。" 在现代微电子系统中，3-D片上网络(NoC)已经成为解决芯片集成度不断提高所引发的通信挑战的关键技术。NoC允许高效的芯片内部数据交换，但随着集成度的提高，热量管理成为了一个重大问题。论文“Thermal-aware Energy Optimization by Synthesizing Firm 3-D Network-on-Chip with Voltage-Frequency Islands”专注于解决这一问题，通过引入电压频率岛策略，可以在不同区域独立地调整电压和频率，以实现能效优化。电压频率岛(VFI)是一种节能策略，它允许在不同部分的芯片上使用不同的电压和频率水平。这种灵活性使得系统能够在满足性能需求的同时，降低功耗。然而，在3-D NoC中应用VFI技术会带来额外的热挑战，因为不同频率和电压的操作可能导致不均匀的热分布，这可能损害芯片的可靠性和性能。为了解决这些问题，论文提出了一个VFI感知的综合框架。该框架不仅考虑了任务调度和电压缩放，还考虑了网络流量的动态变化和热分布的平衡。通过对计算任务的智能分配和电压频率的精细调整，该框架旨在确保系统整体能量消耗的最小化，同时保持温度均衡，防止过热。此外，论文特别强调在硬平台上进行设计，这意味着结构已经被预定义，对优化空间有所限制。为此，该框架提供了一种方法，使设计者能在保持架构约束的同时，自由地决定计算组件如何映射到3-D NoC的不同层，从而增加设计的灵活性。这项工作为3-D NoC的热管理和能源优化提供了新的视角，为未来高密度、高性能的集成电路设计提供了有价值的指导。通过综合考虑任务调度、电压频率控制和热管理，该框架有望在减少能源消耗的同时，增强系统的稳定性和可靠性。

Thermal-aware Energy Optimization by Synthesizing Firm 3-D Network-on-Chip

with Voltage-Frequency Islands

Song Jin

, Jun Liu

,Yu Wang

Department of Electronic and Communication Engineering, School of Electrical and Electronic Engineering,

North China Electric Power University, P. R. China

School of Computer and Information, Hefei University of Technology, Hefei, P. R. China

jinsong@ncepu.edu.cn

liujun@hfut.edu.cn wangyu@ncepu.edu.cn

Abstract—In this paper, we introduce voltage-frequency is-

land (VFI) -based design paradigm into three dimensional (3-D)

network-on-chip (NoC) to optimize system energy. The

prominent challenges to VFI-based 3-D NoC designs are the

exacerbated thermal issues. Moreover, targeting hard

platform with pre-designed structure restrains the

optimization space of the prior work. In view of the above

limitations, we propose a VFI-aware synthesis framework to

minimize system energy and keep thermal balancing for the

ﬁrm 3-D NoC platform where designers have the freedom to

make mapping decisions on computation components. Besides

task scheduling and voltage scaling for computation energy

minimization, core stacking and task migrating algorithm are

proposed to optimize communication energy and balance

powers across the core stacks. By treating each core stack as a

unity, VFI aware 3-D NoC mapping problem can be simpliﬁed

as the mapping issue on 2-D. Experimental results

demonstrate that on average our framework can achieve an

energy reduction of 18.6% over the prior thermal balancing

algorithm. Moreover, on average 5.7 ℃ reduction in peak

temperature is achieved by our framework, compared with the

state-of-art energy optimization scheme.

Keywords- System energy, Voltage-frequency island, 3-

dimensional, System-on-chip

I. INTRODUCTION

With abundant energy efficient interconnects, 3-D

network-on-chip (NoC) brings great potential to build a

complex system with lower system energy [1, 2]. Moreover,

the tile-based NoC structure ﬁts well with the concept of

voltage-frequency island (VFI) [3]-[5], a kind of globally

asynchronous locally synchronous (GALS) design paradigm.

With VFI design, the tiles in NoC are divided into different

islands, and each island can operate at its own voltage and

frequency. Such design style helps to implement ﬁne-grained

system-level power management, thus providing a vigorous

way to build an energy efficient 3-D system.

However, the rigorous thermal issues bring signiﬁcant

challenges on introducing VFI-based design into the 3-D

NoC platform. The increased power density in 3-D stacking

exacerbates hot spot and generates high temperature on the

chip [6]. Heterogeneous workloads executed on 3-D NoC

causes power variation, resulting in the thermal gradient

across the chip. High temperature and thermal gradient not

only degrade system performance and reliability, but also

offset the effort of system energy optimization.

Although VFI-based energy optimizations have been

popularized in 2-D NoC [7]-[10], the more complex thermal

characteristics of 3-D integration prevent them from being

effectively applied to the 3-D platform. On the other hand,

the existing 3-D thermal optimization solutions, either in

hardware [11]-[13] or in software level [14]-[16], generally

did not take VFI-based design into consideration and ignored

energy optimization. Moreover, the prior work commonly

targeted hard NoC platform where both computation and

communication components have been ﬁxed. As a result,

optimization space is inevitably restrained.

To tackle above problems, we propose to synthesize 3-D

NoC with VFI for minimizing system energy meanwhile

keeping thermal balancing across the chip. Unlike prior

work, our synthesis framework targeted ﬁrm NoC platform

where the communication architecture has been pre-designed

but the mapping of the computation components has not

been determined yet [17]. This permits us to uniﬁed consider

NoC mapping and VFI partitioning and enables us to

ﬂexibly explore better thermal-energy optimization tradeoff.

Besides exploiting task scheduling and voltage scaling for

computation energy minimization, core stacking and task

migrating algorithm is proposed to optimize communication

energy and balance powers across the core stacks. By

treating each core stack as a unity, VFI aware 3-D NoC

mapping problem can be simpliﬁed as the mapping issue on

2-D. Experimental results demonstrate that on average our

framework can achieve an energy reduction of 18.6% over

the thermal balancing algorithm. While comparing with the

state-of-art energy optimization schemes, on average 5.7℃

reduction in peak temperature is achieved by our framework.

The rest of the paper is organized as follows. Section

Ⅱ

introduces related work. Section Ⅲ presents the preliminaries

and framework overview. Section

Ⅳ details the proposed

synthesis framework. Section

Ⅴ presents the experimental

results. We conclude in Section

Ⅵ.

II. RELATED

WORK

The large amount of literature has been proposed to

handle thermal issues in 3-D chip. In hardware aspects,

Goplen and Wong separately proposed thermal vias insertion

[11] and placement [12] to reduce the chip temperature.

Bakir et al. [13] proposed to adopt liquid cooling to help heat

dissipation for 3-D ICs. In software aspects, dynamic

thermal management (DPM) technologies were proposed to

restrain thermal emergency at runtime [14]. Zhou et al. [15]

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