飞思卡尔MPC5534微控制器技术规格与优势

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飞思卡尔MPC5534是一款基于Power Architecture嵌入式技术的微控制器，它属于MPC5500系列的一部分。这款高性能的MCU旨在提供大量的新特性，同时通过采用先进的CMOS工艺，显著降低成本并提升性能，相比MPC500系列有显著的升级。 MPC5534的核心处理器符合Power Architecture嵌入式类别标准，这意味着它在用户模式下（包括支持浮点运算库）与原始Power PC指令集完全兼容，这对于需要高性能计算和兼容性的应用来说是个关键优势。它的设计注重于增强嵌入式应用的效率，通过额外的指令集支持，如数字信号处理（DSP），可以高效处理音频、视频信号处理等复杂任务。该微控制器集成了多种功能，包括但不限于高级定时器和计数器，看门狗定时器，以及丰富的中断管理能力，这些都使得它在实时控制、工业自动化、通信和多媒体处理等领域具有广泛的应用潜力。此外，其封装形式和引脚分配信息也在数据手册中详尽列出，以便工程师们进行硬件设计和电路布局。 MPC5534的低功耗特性和高度集成的特性使得它成为物联网(IoT)设备、汽车电子、航空航天和工业控制系统的理想选择。为了获取更深入的设备功能和编程指南，用户应参考MPC5534微控制器参考手册，其中详细介绍了如何利用其内存管理、外设接口、以及片内存储器配置等特性。总结来说，飞思卡尔MPC5534以其强大的性能、广泛的兼容性、丰富的功能集和优化的电源效率，为开发人员提供了一种高效且成本效益高的解决方案，尤其适合那些对速度、灵活性和能效有高要求的嵌入式系统项目。

MPC5534 Microcontroller Data Sheet, Rev. 6

Electrical Characteristics

Freescale Semiconductor10

3.7 Power-Up/Down Sequencing

Power sequencing between the 1.5 V power supply and V

DDSYN

or the RESET power supplies is required

if using an external 1.5 V power supply with V

RC33

tied to ground (GND). To avoid power-sequencing,

RC33

must be powered up within the specified operating range, even if the on-chip voltage regulator

controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and

Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”

Power sequencing requires that V

DD33

must reach a certain voltage where the values are read as ones

before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on

VDD33.”

Although power sequencing is not required between V

RC33

and V

DDSYN

during power up, V

RC33

must

not lead V

DDSYN

by more than 600 mV or lag by more than 100 mV for the V

stage turn-on to operate

within specification. Higher spikes in the emitter current of the pass transistor occur if V

RC33

leads or lags

DDSYN

by more than these amounts. The value of that higher spike in current depends on the board power

supply circuitry and the amount of board level capacitance.

Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase

of the current consumed by V

RC33

. If V

RC33

lags V

DDSYN

by more than 100 mV, the increase in current

consumed can drop V

low enough to assert the 1.5 V POR again. Oscillations are possible when the

1.5 V POR asserts and stops the system clock, causing the voltage on V

to rise until the 1.5 V POR

negates again. All oscillations stop when V

RC33

is powered sufficiently.

9 Absolute value of slew rate on power supply pins — — 50 V/ms

Required gain at Tj:

 I

VRCCTL

(@ f

sys

= f

MAX

)

6, 7,

8, 9

– 40

BETA

35 — —

C40——

150

C50500—

The internal POR signals are V

POR15

, V

POR33

, and V

POR5

. On power up, assert RESET before the internal POR negates.

RESET must remain asserted until the power supplies are within the operating conditions as specified in Ta bl e 9 DC Electrical

Specifications. On power down, assert RESET

before any power supplies fall outside the operating conditions and until the

internal POR asserts.

IL_S

(Ta b l e 9 , Spec15) is guaranteed to scale with V

DDEH6

down to V

POR5

Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.

It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.

At peak current for device.

Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal

traces/routing from the V

RCCTL

package signal to the base of the external pass transistor and between the emitter of the pass

transistor to the V

package signals must have a maximum of 100 nH inductance and minimal resistance

(less than 1 ). V

RCCTL

must have a nominal 1 F phase compensation capacitor to ground. V

must have a 20 F (nominal)

bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of

eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the V

supply signals.

VRCCTL

is measured at the following conditions: V

= 1.35 V, V

RC33

= 3.1 V, V

VRCCTL

= 2.2 V.

Refer to Ta bl e 1 for the maximum operating frequency.

Values are based on I

from high-use applications as explained in the I

Electrical Specification.

BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I

 I

VRCCTL

Table 6. V

and POR Electrical Specifications (continued)

Spec Characteristic Symbol Min. Max. Units

Electrical Characteristics

MPC5534 Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

When powering down, V

RC33

and V

DDSYN

have no delta requirement to each other, because the bypass

capacitors internal and external to the device are already charged. When not powering up or down, no delta

between V

RC33

and V

DDSYN

is required for the V

to operate within specification.

There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current

spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending

on which supplies are powered.

Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).

Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and

pad_sh (slow type).

The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins

during power up.

Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the

internal POR negates, the functional state of the signal during reset applies and the weak-pull devices

(up or down) are enabled as defined in the device reference manual. If V

is too low to correctly

propagate the logic signals, the weak-pull devices can pull the signals to V

DDE

and V

DDEH

To avoid this condition, minimize the ramp time of the V

supply to a time period less than the time

required to enable the external circuitry connected to the device outputs.

During initial power ramp-up, when vstby is 0.6v or above. a typical current of 1-3mA and maximum of

4mA may be seen until V

is applied. This current will not reoccur until V

stby

is lowered below V

stby

min specification.

Table 7. Pin Status for Fast Pads During the Power Sequence

DDE

DD33

POR

Pin Status for Fast Pad Output Driver

pad_fc (fast)

Low — — Asserted Low

DDE

Low Low Asserted High

DDE

Low V

Asserted High

DDE

DD33

Low Asserted High impedance (Hi-Z)

DDE

DD33

Asserted Hi-Z

DDE

DD33

Negated Functional

Table 8. Pin Status for Medium and Slow Pads During the Power Sequence

DDEH

POR

Pin Status for Medium and Slow Pad Output Driver

pad_mh (medium) pad_sh (slow)

Low — Asserted Low

DDEH

Low Asserted High impedance (Hi-Z)

DDEH

Asserted Hi-Z

DDEH

Negated Functional

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