Verilog黄金参考手册：快速设计与应用指南

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Verilog黄金指南是一份由Doulos公司编撰的权威指南，专注于Verilog硬件描述语言（HDL）的快速参考。Verilog是Cadence Design Systems Inc.注册的商标，它是一种广泛用于数字电路设计、验证和实现的高级硬件描述语言，尤其在现代集成电路设计中扮演着关键角色。该指南的主要目的是为Verilog的用户和开发者提供一个便于查阅的实用工具，它并非替代IEEE标准的Verilog语言参考手册。与详尽的规范手册不同，黄金参考指南侧重于实际应用中的语法、语义解释以及设计流程中的具体指导。它涵盖了以下关键知识点： 1. **语言概述**：介绍Verilog的基本概念，包括其设计目的、特点和在电子设计自动化（EDA）中的地位。 2. **语法结构**：详细解析Verilog的文本式和数据流两种编程模式，包括模块化设计（模块、端口、参数等）、过程语句（if、case、always等）、数据类型和数据流控制结构。 3. **逻辑描述**：阐述如何用Verilog编写组合逻辑和时序逻辑电路，如门级描述、函数和表达式、触发器等。 4. **仿真和验证**：指南可能包括如何设置和运行Verilog仿真，以及如何使用测试bench进行功能和时序验证。 5. **综合与映射**：讲解Verilog代码如何转化为可制造的硬件描述，涉及综合工具、逻辑优化和映射策略。 6. **应用实例**：提供一系列实例，帮助读者理解和实践各种设计技巧，包括设计接口、处理并行和流水线结构等。 7. **最佳实践**：针对设计效率和可维护性，给出一些建议和注意事项，如模块化设计原则、避免潜在的陷阱等。 8. **版权和使用许可**：明确指出未经Doulos许可，任何形式的复制、存储或传输都需要事先书面授权，强调了版权法律的严谨性。 Verilog黄金指南是工程师们的必备参考资料，无论是在学习Verilog语言基础，还是在进行实际项目设计时遇到问题，都可以从中找到快速和实用的答案。通过阅读和使用这份指南，设计师可以提升他们的硬件描述技能，加速产品开发进程。

A statement which conditionally executes at most one branch, depending on

the value of the case expression.

Syntax

CaseKeyword

(

Expression

)

Expression,...

Statement

{Expression may be variable}

Expression,...

Statement

... {Any number of cases}

[default [:]

Statement

] {Need not be at the end}

endcase

CaseKeyword =

{either} case casex casez

Where

See Statement.

Rules

Xs and Zs in a casex statement, and Zs in a casez statement mean “don’t

care”.

One default statement at most may be included. It is executed if no label

expressions match the case expression. (A ‘label’ is an expression or a

comma-separated list of expressions on the left of a colon, or the reserved

word default, which may or may not be followed by a colon.)

Where a label is a comma-separated list of two or more expressions, the label

is matched if the case expression matches any one of the label expressions.

If no label expressions match the case expression and there is no default

statement, the case statement has no effect.

Gotchas!

If more than one statement is to be executed for a particular label, the

statements must be enclosed in a begin-end or fork-join block.

A branch is only executed if the corresponding label is the first one to match

the case expression. Case labels need not be mutually exclusive, so a

Verilog compiler will not report an error where the same label has erroneously

been repeated.

The syntax of a casex or casez statement ends with the reserved word

endcase, not endcasex or endcasez.

An X or Z in the casex expression or a Z in a casez expression is matched

with any value in a case label. This may give confusing simulation results.

Synthesis

Assignments within case statements generally synthesize to multiplexers. If

variables (i.e. registers or nets) are used for case labels, priority encoders

may be synthesized.

Case

Coding standards are divided into two categories. Lexical coding standards,

which control text layout, naming conventions and commenting, are intended

to improve readability and ease of maintenance. Synthesis coding standards,

which control Verilog style, are intended to avoid common synthesis pitfalls

and find synthesis errors early in the design flow.

The following lists of coding standards will need to be modified according to

the choice of tools and personal preferences.

Lexical Coding Standards

Limit the contents of each Verilog source file to one module, and do not split

modules across files.

Source file names should relate to the file contents (e.g. ModuleName.v).

Write only one declaration or statement per line.

Use indentation as shown in the examples.

Be consistent about the case of user defined names (e.g. first letter a capital).

User defined names should be meaningful and informative, although local

names (e.g. loop variables) may be terse.

Write comments to explain (not duplicate) the Verilog code. It is particularly

important to comment interfaces (e.g. module parameters, ports, task and

function arguments).

Use parameters or `define macros wherever possible, instead of directly

embedding literal numbers and strings in declarations and statements.

Synthesis Coding Standards

Partition the design into small functional blocks, and use a behavioural style

for each block. Avoid gate level descriptions except for critical parts of the

design.

Have a well defined clocking strategy, and implement that strategy explicitly in

Verilog (e.g. single clock, multi-phase clocks, gated clocks, multiple clock

domains). Ensure that clock and reset signals in Verilog are clean (i.e. not

generated from combinational logic or unintentionally gated).

Have a well defined (manufacturing) testing strategy, and code up the Verilog

appropriately (e.g. all flipflops resettable, test access from external pins, no

functional redundancy).

Every Verilog always should conform to one of the standard synthesizable

process templates (see

Always

An always describing combinational and latched logic must have all of the

inputs in the event control list at the top of the always.

A combinational always must not contain incomplete assignments, i.e. all

outputs must be assigned for all combinations of input values.

An always describing combinational and latched logic must not contain

feedback, i.e. registers assigned as outputs from the always must not be

read as inputs to the always.

Coding Standards

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