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首页TMS320x2806x Piccolo TRM:系统控制与安全指南
TMS320x2806x Piccolo TRM:系统控制与安全指南
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更新于2024-07-20
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TMS28069是一款针对低功耗和安全应用设计的TMS320x2806x系列的Piccolo微控制器的技术参考手册。该手册于2011年首次发布,并在2014年进行了修订,提供了全面深入的硬件和软件设计指南。
首先,系统控制和中断是核心部分,包括对闪存和片外只读存储器(OTP)块的操作。闪存作为非易失性存储,用于长期保存用户程序和数据,而OTP则用于存放固定的配置信息,如安全密钥或固件版本。手册详细解释了不同类型的存储器的电源模式管理和相关寄存器操作,确保了数据的安全性和可靠性。
代码安全模块(CSM)是TMS28069的一个关键特性,其功能着重于保护芯片内部逻辑免受恶意攻击。CSM通过功能描述、对其他芯片资源的影响、以及如何在用户应用中整合来确保代码的完整性。指南列出了保护安全逻辑的最佳实践,并总结了CSM的主要特性和优势。
此外,手册还涵盖了时钟管理,这是微控制器正常运行的基础。它阐述了时钟和系统控制的机制,包括振荡器(OSC)和锁相环路(PLL)的使用,以及在不同低功耗模式下的性能优化。还包括CPU watchdog定时器和32位CPU定时器0/1/2的功能和配置。
通用输入/输出(GPIO)模块是TMS28069的重要I/O接口,用于处理数字信号的输入和输出。手册介绍了GPIO模块的概述、配置选项、控制逻辑、输入资格检测以及与外围设备的多路复用功能。同时,它提供了详细的寄存器定义,帮助开发者理解和利用GPIO的全部潜力。
最后,手册还涉及了外围框(Peripheral Frame)的概念,这是一种组织和管理外部设备连接的方式。它包含帧寄存器的说明,以及如何通过EALLOW引脚进行权限控制,确保了系统的可靠性和安全性。
TMS28069技术参考手册为开发人员提供了关于这款低功耗、安全型微控制器的全面指南,无论是对硬件配置、软件开发,还是系统安全,都能提供所需的知识和信息。对于想要深入理解并有效利用这款器件的工程师来说,这是一份不可或缺的参考资料。
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1-97. Debug Interrupt Enable Register (DBGIER) — CPU Register ..................................................... 185
1-98. External Interrupt n Control Register (XINTnCR) .................................................................... 187
1-99. External Interrupt n Counter (XINTnCTR) (Address 7078h) ........................................................ 188
1-100. BOR Configuration (BORCFG) Register .............................................................................. 190
2-1. Memory Map of On-Chip ROM ......................................................................................... 192
2-2. Vector Table Map......................................................................................................... 196
2-3. Bootloader Flow Diagram................................................................................................ 199
2-4. Boot ROM Stack .......................................................................................................... 201
2-5. Boot ROM Function Overview .......................................................................................... 203
2-6. Bootloader Basic Transfer Procedure ................................................................................. 215
2-7. Overview of InitBoot Assembly Function .............................................................................. 216
2-8. Overview of the SelectBootMode Function ........................................................................... 217
2-9. Overview of Get_mode() Function ..................................................................................... 218
2-10. Overview of CopyData Function ....................................................................................... 219
2-11. Overview of SCI Bootloader Operation ................................................................................ 219
2-12. Overview of SCI_Boot Function ........................................................................................ 220
2-13. Overview of SCI_GetWordData Function ............................................................................. 221
2-14. Overview of Parallel GPIO bootloader Operation .................................................................... 221
2-15. Parallel GPIO Boot Loader Handshake Protocol ..................................................................... 222
2-16. Parallel GPIO Mode Overview .......................................................................................... 223
2-17. Parallel GPIO Mode - Host Transfer Flow............................................................................. 224
2-18. 8-Bit Parallel GetWord Function ........................................................................................ 225
2-19. SPI Loader................................................................................................................. 226
2-20. Data Transfer From EEPROM Flow.................................................................................... 228
2-21. Overview of SPIA_GetWordData Function ........................................................................... 228
2-22. EEPROM Device at Address 0x50 ..................................................................................... 229
2-23. Overview of I2C_Boot Function ........................................................................................ 230
2-24. Random Read............................................................................................................. 231
2-25. Sequential Read .......................................................................................................... 231
2-26. Overview of eCAN-A bootloader Operation ........................................................................... 232
2-27. ExitBoot Procedure Flow ................................................................................................ 234
3-1. Multiple ePWM Modules ................................................................................................. 243
3-2. Submodules and Signal Connections for an ePWM Module........................................................ 244
3-3. ePWM Submodules and Critical Internal Signal Interconnects..................................................... 245
3-4. Time-Base Submodule Block Diagram ................................................................................ 250
3-5. Time-Base Submodule Signals and Registers........................................................................ 251
3-6. Time-Base Frequency and Period...................................................................................... 253
3-7. Time-Base Counter Synchronization Scheme 1...................................................................... 255
3-8. Time-Base Counter Synchronization Scheme 2...................................................................... 256
3-9. Time-Base Counter Synchronization Scheme 3...................................................................... 257
3-10. Time-Base Up-Count Mode Waveforms............................................................................... 259
3-11. Time-Base Down-Count Mode Waveforms ........................................................................... 260
3-12. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event .... 260
3-13. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event........ 261
3-14. Counter-Compare Submodule .......................................................................................... 261
3-15. Detailed View of the Counter-Compare Submodule ................................................................. 263
3-16. Counter-Compare Event Waveforms in Up-Count Mode............................................................ 265
3-17. Counter-Compare Events in Down-Count Mode ..................................................................... 266
3-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
16
List of Figures SPRUH18E–January 2011–Revised March 2014
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Synchronization Event ................................................................................................... 267
3-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ....................................................................................................................... 267
3-20. Action-Qualifier Submodule ............................................................................................. 268
3-21. Action-Qualifier Submodule Inputs and Outputs...................................................................... 269
3-22. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ........................................... 270
3-23. Up-Down-Count Mode Symmetrical Waveform....................................................................... 273
3-24. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................. 274
3-25. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................... 275
3-26. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA............. 276
3-27. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................. 278
3-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ........................................................................................... 279
3-29. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ......................................................................................................................... 280
3-30. Dead_Band Submodule.................................................................................................. 281
3-31. Configuration Options for the Dead-Band Submodule............................................................... 282
3-32. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 284
3-33. PWM-Chopper Submodule .............................................................................................. 286
3-34. PWM-Chopper Submodule Operational Details ...................................................................... 287
3-35. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 287
3-36. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ....... 288
3-37. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ...................................................................................................................... 289
3-38. Trip-Zone Submodule .................................................................................................... 290
3-39. Trip-Zone Submodule Mode Control Logic............................................................................ 294
3-40. Trip-Zone Submodule Interrupt Logic .................................................................................. 295
3-41. Event-Trigger Submodule ............................................................................................... 296
3-42. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion ........................................ 296
3-43. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................ 297
3-44. Event-Trigger Interrupt Generator ...................................................................................... 298
3-45. Event-Trigger SOCA Pulse Generator ................................................................................. 299
3-46. Event-Trigger SOCB Pulse Generator ................................................................................. 299
3-47. Digital-Compare Submodule High-Level Block Diagram ............................................................ 300
3-48. DCAEVT1 Event Triggering ............................................................................................. 302
3-49. DCAEVT2 Event Triggering ............................................................................................. 302
3-50. DCBEVT1 Event Triggering ............................................................................................. 303
3-51. DCBEVT2 Event Triggering ............................................................................................. 303
3-52. Event Filtering ............................................................................................................. 304
3-53. Blanking Window Timing Diagram...................................................................................... 305
3-54. Simplified ePWM Module ................................................................................................ 306
3-55. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ...................................... 307
3-56. Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
.................................................... 308
3-57. Buck Waveforms for (Note: Only three bucks shown here)......................................................... 309
3-58. Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
) ............................................................. 311
3-59. Buck Waveforms for (Note: F
PWM2
= F
PWM1)
) ............................................................................ 312
3-60. Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
) ........................................................... 314
3-61. Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
) ........................................................... 315
17
SPRUH18E–January 2011–Revised March 2014 List of Figures
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3-62. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control............................... 317
3-63. 3-Phase Inverter Waveforms for (Only One Inverter Shown)....................................................... 318
3-64. Configuring Two PWM Modules for Phase Control .................................................................. 320
3-65. Timing Waveforms Associated With Phase Control Between 2 Modules ......................................... 321
3-66. Control of a 3-Phase Interleaved DC/DC Converter ................................................................. 322
3-67. 3-Phase Interleaved DC/DC Converter Waveforms for ............................................................. 323
3-68. Controlling a Full-H Bridge Stage (F
PWM2
= F
PWM1)
.................................................................... 325
3-69. ZVS Full-H Bridge Waveforms .......................................................................................... 326
3-70. Peak Current Mode Control of a Buck Converter .................................................................... 328
3-71. Peak Current Mode Control Waveforms for .......................................................................... 328
3-72. Control of Two Resonant Converter Stages .......................................................................... 330
3-73. H-Bridge LLC Resonant Converter PWM Waveforms ............................................................... 330
3-74. Time-Base Period Register (TBPRD) .................................................................................. 332
3-75. Time Base Period High Resolution Register (TBPRDHR) .......................................................... 332
3-76. Time Base Period Mirror Register (TBPRDM) ........................................................................ 332
3-77. Time-Base Period High Resolution Mirror Register (TBPRDHRM) ............................................... 333
3-78. Time-Base Phase Register (TBPHS) .................................................................................. 333
3-79. Time-Base Phase High Resolution Register (TBPHSHR)........................................................... 334
3-80. Time-Base Counter Register (TBCTR) ................................................................................ 334
3-81. Time-Base Control Register (TBCTL).................................................................................. 334
3-82. Time-Base Status Register (TBSTS)................................................................................... 337
3-83. High Resolution Period Control Register (HRPCTL)................................................................. 337
3-84. Counter-Compare A Register (CMPA) ................................................................................ 339
3-85. Counter-Compare B Register (CMPB)................................................................................. 339
3-86. Counter-Compare Control Register (CMPCTL)....................................................................... 341
3-87. Compare A High Resolution Register (CMPAHR) ................................................................... 342
3-88. Counter-Compare A Mirror Register (CMPAM) ...................................................................... 342
3-89. Compare A High Resolution Mirror Register .......................................................................... 342
3-90. Action-Qualifier Output A Control Register (AQCTLA)............................................................... 343
3-91. Action-Qualifier Output B Control Register (AQCTLB)............................................................... 344
3-92. Action-Qualifier Software Force Register (AQSFRC) ................................................................ 345
3-93. Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................ 346
3-94. Dead-Band Generator Control Register (DBCTL).................................................................... 347
3-95. Dead-Band Generator Rising Edge Delay Register (DBRED)...................................................... 348
3-96. Dead-Band Generator Falling Edge Delay Register (DBFED) ..................................................... 348
3-97. PWM-Chopper Control Register (PCCTL)............................................................................. 349
3-98. Trip-Zone Select Register (TZSEL) .................................................................................... 351
3-99. Trip-Zone Control Register (TZCTL) ................................................................................... 352
3-100. Trip-Zone Enable Interrupt Register (TZEINT)........................................................................ 353
3-101. Trip-Zone Flag Register (TZFLG)....................................................................................... 354
3-102. Trip-Zone Clear Register (TZCLR) ..................................................................................... 355
3-103. Trip-Zone Force Register (TZFRC)..................................................................................... 355
3-104. Trip Zone Digital Compare Event Select Register (TZDCSEL)..................................................... 356
3-105. Digital Compare Trip Select (DCTRIPSEL) ........................................................................... 358
3-106. Digital Compare A Control Register (DCACTL) ...................................................................... 359
3-107. Digital Compare B Control Register (DCBCTL)....................................................................... 360
3-108. Digital Compare Filter Control Register (DCFCTL) .................................................................. 360
3-109. Digital Compare Capture Control Register (DCCAPCTL) ........................................................... 361
3-110. Digital Compare Counter Capture Register (DCCAP) ............................................................... 361
18
List of Figures SPRUH18E–January 2011–Revised March 2014
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3-111. Digital Compare Filter Offset Register (DCFOFFSET) .............................................................. 362
3-112. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) .............................................. 362
3-113. Digital Compare Filter Window Register (DCFWINDOW)........................................................... 363
3-114. Digital Compare Filter Window Counter Register (DCFWINDOWCNT)........................................... 363
3-115. Event-Trigger Selection Register (ETSEL) ............................................................................ 363
3-116. Event-Trigger Prescale Register (ETPS) .............................................................................. 365
3-117. Event-Trigger Flag Register (ETFLG).................................................................................. 366
3-118. Event-Trigger Clear Register (ETCLR) ................................................................................ 367
3-119. Event-Trigger Force Register (ETFRC)................................................................................ 367
4-1. Resolution Calculations for Conventionally Generated PWM....................................................... 371
4-2. Operating Logic Using MEP............................................................................................. 373
4-3. HRPWM Extension Registers and Memory Configuration .......................................................... 374
4-4. HRPWM System Interface............................................................................................... 375
4-5. HRPWM Block Diagram ................................................................................................. 376
4-6. Required PWM Waveform for a Requested Duty = 30.0% ......................................................... 378
4-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................. 381
4-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ........................................... 383
4-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)........................................... 383
4-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ................................... 384
4-11. Simple Buck Controlled Converter Using a Single PWM............................................................ 388
4-12. PWM Waveform Generated for Simple Buck Controlled Converter ............................................... 388
4-13. Simple Reconstruction Filter for a PWM Based DAC................................................................ 390
4-14. PWM Waveform Generated for the PWM DAC Function ........................................................... 390
4-15. HRPWM Configuration Register (HRCNFG) .......................................................................... 394
4-16. Counter Compare A High Resolution Register (CMPAHR) ......................................................... 395
4-17. TB Phase High Resolution Register (TBPHSHR) .................................................................... 395
4-18. Time Base Period High Resolution Register .......................................................................... 395
4-19. Compare A High Resolution Mirror Register .......................................................................... 396
4-20. Time-Base Period High Resolution Mirror Register .................................................................. 396
4-21. High Resolution Period Control Register (HRPCTL)................................................................. 396
4-22. High Resolution Micro Step Register (HRMSTEP) (EALLOW protected): ........................................ 397
5-1. HRCAP Module System Block Diagram ............................................................................... 403
5-2. HRCAP Block Diagram .................................................................................................. 404
5-3. HCCAPCLK Generation ................................................................................................. 404
5-4. HCCOUNTER Behavior During High Pulse Width Capture......................................................... 405
5-5. Rise vs. Fall Capture Events ............................................................................................ 406
5-6. High Pulse Width Normal Mode Capture .............................................................................. 407
5-7. Low Pulse Width Normal Mode Capture............................................................................... 407
5-8. HRCAP High-Resolution Mode Operating Logic ..................................................................... 408
5-9. Interrupts in HRCAP Module ............................................................................................ 408
5-10. HRCAP Control Register (HCCTL) .................................................................................... 409
5-11. HRCAP Interrupt Flag Register (HCIFR) .............................................................................. 410
5-12. HRCAP Interrupt Clear Register (HCICLR) ........................................................................... 411
5-13. HRCAP Interrupt Force Register (HCIFRC) .......................................................................... 412
5-14. HRCAP Counter Register (HCCOUNTER)............................................................................ 412
5-15. HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0)...................................... 413
5-16. HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1)...................................... 413
5-17. HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0) ..................................... 413
5-18. HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1) ..................................... 414
19
SPRUH18E–January 2011–Revised March 2014 List of Figures
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5-19. LowPulseWidth0 Capture on RISE and FALL Events ............................................................... 416
5-20. HighPulseWidth0/1 Capture on RISE and FALL Events ............................................................ 417
5-21. PeriodWidthRise0 and PeriodWidthFall0 Capture on RISE and FALL Events ................................... 418
6-1. Capture and APWM Modes of Operation.............................................................................. 424
6-2. Capture Function Diagram............................................................................................... 425
6-3. Event Prescale Control................................................................................................... 426
6-4. Prescale Function Waveforms .......................................................................................... 426
6-5. Details of the Continuous/One-shot Block............................................................................. 427
6-6. Details of the Counter and Synchronization Block ................................................................... 428
6-7. Interrupts in eCAP Module .............................................................................................. 429
6-8. PWM Waveform Details Of APWM Mode Operation ................................................................ 430
6-9. Time-Stamp Counter Register (TSCTR)............................................................................... 431
6-10. Counter Phase Control Register (CTRPHS) ......................................................................... 431
6-11. Capture-1 Register (CAP1) ............................................................................................. 431
6-12. Capture-2 Register (CAP2).............................................................................................. 431
6-13. Capture-3 Register (CAP3).............................................................................................. 432
6-14. Capture-4 Register (CAP4).............................................................................................. 432
6-15. ECAP Control Register 1 (ECCTL1) ................................................................................... 432
6-16. ECAP Control Register 2 (ECCTL2) ................................................................................... 433
6-17. ECAP Interrupt Enable Register (ECEINT)............................................................................ 436
6-18. ECAP Interrupt Flag Register (ECFLG)................................................................................ 437
6-19. ECAP Interrupt Clear Register (ECCLR) .............................................................................. 437
6-20. ECAP Interrupt Forcing Register (ECFRC)............................................................................ 438
6-21. Capture Sequence for Absolute Time-stamp and Rising Edge Detect ............................................ 441
6-22. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................. 443
6-23. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect......................................... 445
6-24. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect.......................... 447
6-25. PWM Waveform Details of APWM Mode Operation ................................................................. 449
7-1. Optical Encoder Disk ..................................................................................................... 452
7-2. QEP Encoder Output Signal for Forward/Reverse Movement...................................................... 452
7-3. Index Pulse Example..................................................................................................... 453
7-4. Functional Block Diagram of the eQEP Peripheral................................................................... 455
7-5. Functional Block Diagram of Decoder Unit............................................................................ 457
7-6. Quadrature Decoder State Machine.................................................................................... 458
7-7. Quadrature-clock and Direction Decoding............................................................................. 459
7-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) ............... 461
7-9. Position Counter Underflow/Overflow (QPOSMAX = 4) ............................................................ 462
7-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)................................................. 464
7-11. Strobe Event Latch (QEPCTL[SEL] = 1)............................................................................... 464
7-12. eQEP Position-compare Unit............................................................................................ 465
7-13. eQEP Position-compare Event Generation Points ................................................................... 466
7-14. eQEP Position-compare Sync Output Pulse Stretcher .............................................................. 466
7-15. eQEP Edge Capture Unit ................................................................................................ 468
7-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) .................................. 468
7-17. eQEP Edge Capture Unit - Timing Details ............................................................................ 469
7-18. eQEP Watchdog Timer .................................................................................................. 470
7-19. eQEP Unit Time Base.................................................................................................... 470
7-20. EQEP Interrupt Generation.............................................................................................. 471
7-21. QEP Decoder Control (QDECCTL) Register.......................................................................... 471
20
List of Figures SPRUH18E–January 2011–Revised March 2014
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