AMD AM186CC: 高性能80C186兼容嵌入式通信控制器规格

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"AM186CC是一款由AMD公司生产的高性能、与80C186兼容的16位嵌入式通信控制器。这款芯片在2000年发布，具有独特的特性，包括与E86系列x86嵌入式处理器的兼容性，提供软件迁移便利，并配备了世界一流的开发工具和系统软件。此外，AM186CC强调了其在串行通信外设方面的优势，如四个高级数据链路控制（HDLC）通道、四个独立的时间槽分配器（TSAs）、物理接口支持HDLC通道，以及USB外围控制器。其他特性还包括高速UART、同步串行接口（SSI）和SmartDMA通道，用于支持USB和HDLC。系统级外设方面，AM186CC提供了三个可编程16位定时器、硬件看门狗定时器、通用DMA（4个通道）、48个可编程输入/输出信号（PIO）和中断控制器（36个可屏蔽中断）。内存和外围接口部分，集成的DRAM控制器和无胶合逻辑接口到RAM/ROM/Flash内存，支持55-ns Flash等不同类型的存储设备。" AM186CC是AMD推出的一款专为嵌入式系统设计的微处理器，其核心特性在于其与80C186的兼容性，这意味着软件开发者可以轻松地将基于80C186的代码迁移到AM186CC上，减少了开发时间和成本。同时，AMD提供的世界级别的开发工具和应用软件为开发者提供了强大的支持。在通信功能上，AM186CC非常强大，它包含四个HDLC通道，这使得它能够处理多种通信协议，如PPP、X.25等。四个独立的时间槽分配器（TSAs）允许高效的多路复用，提高通信效率。物理接口的灵活性使其能够适应不同的通信标准，如DCE、PCM高速公路或GCI（IOM-2）。此外，AM186CC还集成了USB外围控制器，以满足现代设备对高速数据传输的需求。智能DMA通道是AM186CC的一个亮点，它有8个这样的通道，专门设计用来支持USB和HDLC的高效数据传输，显著提高了系统的吞吐量。高速UART支持自动波特率检测，增强了与各种串行设备的连接能力。同步串行接口（SSI）则适用于需要精确同步的数据传输场景。在系统级外设方面，AM186CC提供了一系列丰富的功能，包括三个可编程16位定时器，可以用于计时、定时触发任务等；硬件看门狗定时器确保系统在异常情况下能恢复稳定状态；4个通用DMA通道可以加速数据传输，减轻CPU负担；48个可编程输入/输出信号（PIO）允许灵活配置系统接口；而36个可屏蔽中断控制器则为系统提供了复杂的中断管理机制。最后，在内存和外围接口方面，AM186CC内置了DRAM控制器，简化了内存管理，且无胶合逻辑接口可以直接与各种内存类型配合，包括快速闪存，提升了系统的扩展性和灵活性。 AM186CC是一款集成了丰富通信和系统功能的微处理器，特别适合需要高效、可靠通信和复杂系统管理的嵌入式应用。其兼容性、高性能和广泛的外设支持使其成为工业自动化、网络设备、数据采集等多个领域的理想选择。

16 Am186™CC Communications Controller Data Sheet

HLDA {CLKSEL1} O Bus-Hold Acknowledge is asserted to indicate to an external bus master that

the Am186CC controller has relinquished control of the local bus. When an

external bus master requests control of the local bus (by asserting HOLD), the

microcontroller completes the bus cycle in progress, then relinquishes control of

the bus to the external bus master by asserting HLDA and three-stating S2–S0,

AD15–AD0, S6, and A19–A0. The following are also three-stated and have

pullups: UCS

, LCS, MCS3–MCS0, PCS7–PCS0, DEN, RD, WR, BHE, WHB,

WLB

, and DT/R. ALE is three-stated and has a pulldown.

When the external bus master has finished using the local bus, it indicates this

to the Am186CC controller by deasserting HOLD. The controller responds by

deasserting HLDA.

If the Am186CC controller requires access to the bus (for example, for refresh),

the controller deasserts HLDA before the external bus master deasserts HOLD.

The external bus master must be able to deassert HOLD and allow the controller

access to the bus. See the timing diagrams for bus hold on page 70.

HOLD — STI Bus-Hold Request indicates to the Am186CC controller that an external bus

master needs control of the local bus.

The Am186CC controller’s HOLD latency time—the time between HOLD

request and HOLD acknowledge—is a function of the activity occurring in the

processor when the HOLD request is received. A HOLD request is second only

to DRAM refresh requests in priority of activity requests received by the

processor. This implies that if a HOLD request is received just as a DMA transfer

begins, the HOLD latency can be as great as four bus cycles. This occurs if a

DMA word transfer operation is taking place from an odd address to an odd

address. This is a total of 16 clock cycles or more if wait states are required. In

addition, if locked transfers are performed, the HOLD latency time is increased

by the length of the locked transfer. HOLD latency is also potentially increased

by DRAM refreshes.

The board designer is responsible for properly terminating the HOLD input.

For more information, see the HLDA pin description.

—ORead Strobe indicates to the system that the Am186CC controller is performing

a memory or I/O read cycle. RD

is guaranteed to not be asserted before the

address and data bus is three-stated during the address-to-data transition. RD

is three-stated with a pullup during bus-hold or reset conditions.

S6 — O Bus Cycle Status Bit 6: This signal is asserted during t

–t

to indicate a DMA-

initiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and

three-stated with a pulldown during reset.

SRDY [PIO35] STI Synchronous Ready indicates to the Am186CC controller that the addressed

memory space or I/O device will complete a data transfer. The SRDY pin accepts

an active High input synchronized to CLKOUT.

Using SRDY instead of ARDY allows a relaxed system timing because of the

elimination of the one-half clock period required to internally synchronize ARDY.

To always assert the ready condition to the microcontroller, tie SRDY High. If the

system does not use SRDY, tie the pin Low to yield control to ARDY.

Table 4. Signal Descriptions (Continued)

Signal Name

Multiplexed

Signal(s)

Type Description

Am186™CC Communications Controller Data Sheet 17

—

{USBXCVR}

O Bus Cycle Status 2–0 indicate to the system the type of bus cycle in progress.

2 can be used as a logical memory or I/O indicator, and S1 can be used as a

data transmit or receive indicator. S

2–S0 are three-stated during bus hold and

three-stated with a pullup during reset. The S

2–S0 pins are encoded as follows:

WHB

WLB

—

Write High Byte and Write Low Byte indicate to the system which bytes of the

data bus (upper, lower, or both) participate in a write cycle. In 80C186

microcontroller designs, this information is provided by BHE

, AD0, and WR.

However, by using WHB

and WLB, the standard system interface logic and

external address latch that were required are eliminated.

WHB

is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This

pin is three-stated with a pullup during bus-hold or reset conditions.

WLB

is asserted with AD7–AD0. WLB is the logical AND of AD0 and WR. This

pin is three-stated with a pullup during bus-hold or reset conditions.

[PIO15] O Write Strobe indicates to the system that the data on the bus is to be written to

a memory or I/O device. WR

is three-stated with a pullup during bus-hold or reset

conditions.

CLOCKS/RESET/WATCHDOG TIMER

CLKOUT — O Clock Output supplies the clock to the system. Depending on the values of the

CPU mode select pinstraps, {CLKSEL1} and {CLKSEL2}, CLKOUT operates at

either the PLL frequency or the source input frequency during PLL Bypass

mode. (See Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.)

CLKOUT remains active during bus-hold or reset conditions.

The DISCLK bit in the SYSCON register can be set to disable the CLKOUT

signal. Refer to the

Am186™CC/CH/CU Microcontrollers Register Set Manual

(order #21916).

All synchronous AC timing specifications not associated with SSI, HDLCs,

UARTs, and the USB are synchronous to CLKOUT.

Table 4. Signal Descriptions (Continued)

Signal Name

Multiplexed

Signal(s)

Type Description

Bus Status Pins

S1 S0 Bus Cycle

0 0 0 Reserved

0 0 1 Read data from I/O

0 1 0 Write data to I/O

011Halt

1 0 0 Instruction fetch

1 0 1 Read data from memory

1 1 0 Write data to memory

1 1 1 None (passive)

18 Am186™CC Communications Controller Data Sheet

RES —STIReset requires the Am186CC controller to perform a reset. When RES is

asserted, the controller immediately terminates its present activity, clears its

internal logic, and on the deassertion of RES, transfers CPU control to the reset

address FFFF0h.

RES

must be asserted for at least 1 ms to allow the internal circuits to stabilize.

RES can be asserted asynchronously to CLKOUT because RES is synchronized

internally. For proper initialization, V

must be within specifications, and

CLKOUT must be stable for more than four CLKOUT periods during which RES

is asserted.

If RES

is asserted while the watchdog timer is performing a watchdog-timer reset,

the external reset takes precedence over the watchdog-timer reset. This means

that the RESOUT signal asserts as with any external reset and the WDTCON

based on the external reset timing, i.e., 4.5 clocks after the deassertion of RES

rather than 2

clocks after the watchdog timer timeout occurred.

The Am186CC controller begins fetching instructions approximately 6.5

CLKOUT periods after RES

is deasserted. This input is provided with a Schmitt

trigger to facilitate power-on RES

generation via an RC network.

RESOUT — O Reset Out indicates that the Am186CC

controller is being reset (either

externally or internally), and the signal can be used as a system reset to reset

any external peripherals connected to RESOUT.

During an external reset, RESOUT remains active (High) for two clocks after

RES

is deasserted. The controller exits reset and begins the first valid bus cycle

approximately 4.5 clocks after RES

is deasserted.

[UCLK] [USBSOF]

[USBSCI]

PIO21

STI UART Clock can be used instead of the processor clock as the source clock for

either the UART or the High-Speed UART. The source clock for the UART and

the High-Speed UART are selected independently and both can use the same

source.

USBX1

USBX2

—

STI

USB Controller Crystal Input (USBX1) and USB Controller Crystal Output

(USBX2) provide connections for a fundamental mode, parallel-resonant crystal

used by the internal USB oscillator circuit.

If the CPU crystal is used to generate the USB clock, USBX1 must be pulled down.

—

STI

CPU Crystal Input (X1) and CPU Crystal Output (X2) provide connections for

a fundamental mode, parallel-resonant crystal used by the internal oscillator

circuit. If an external oscillator is used, inject the signal directly into X1 and leave

X2 floating.

PINSTRAPS (See Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.)

RESERVED

RSVD_101

RSVD_102

RSVD_103

RSVD_104

UTXDPLS

UTXDMNS

UXVOE

UXVRCV

—

RSVD_101–RSVD_104 are reserved unless pinstrap {USBXCVR

} is sampled

Low on the rising edge of RESET. When reserved, these pins should not be

connected.

Table 4. Signal Descriptions (Continued)

Signal Name

Multiplexed

Signal(s)

Type Description

Am186™CC Communications Controller Data Sheet 19

POWER AND GROUND

(15) —STIDigital Power Supply pins supply power (+3.3 ± 0.3 V) to the Am186CC

controller logic.

_A (1) — STI Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and

PLLs.

_USB (1) — STI USB Power Supply pin supplies power (+3.3 ± 0.3 V) to the USB block.

(15) — STI Digital Ground pins connect the Am186CC controller logic to the system

ground.

_A (1) — STI Analog Ground pin connects the oscillators and PLLs to the system ground.

_USB (1) — STI USB Ground pin connects the USB block to the system ground.

DEBUG SUPPORT

QS1–QS0 — O Queue Status 1–0 values provide information to the system concerning the

interaction of the CPU and the instruction queue. The pins have the following

meanings:

The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN

}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,

CLKOUT, {CLKSEL2

–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,

RESOUT, S2

–S0, S6, SRDY, UCS, {UCSX8}, V

, WHB, WLB, WR. See the

Am186™CC/CH/CU Microcontrollers User’s

Manual

, order #21914, for more information.

CHIP SELECTS

LCS

[RAS0]OLower Memory Chip Select indicates to the system that a memory access is in

progress to the lower memory block. The base address and size of the lower

memory block are programmable up to 512 Kbyte. LCS can be configured for 8-

bit or 16-bit bus size. LCS

is three-stated with a pullup resistor during bus-hold

or reset conditions.

[MCS3

]

MCS2

MCS1

[MCS0]

[RAS1

]

PIO5

[CAS0

]

[CAS1]

{UCSX8}

PIO4

O Midrange Memory Chip Selects 3–0 indicate to the system that a memory

access is in progress to the corresponding region of the midrange memory block.

The base address and size of the midrange memory block are programmable.

The midrange chip selects can be configured for 8-bit or 16-bit bus size. The

midrange chip selects are three-stated with pullup resistors during bus-hold or

reset conditions.

[MCS0

] can be programmed as the chip select for the entire middle chip select

address range.

Unlike the UCS

and LCS chip selects that operate relative to the earlier timing of

the nonmultiplexed A address bus, the MCS

outputs assert with the multiplexed

AD address and data bus timing.

Table 4. Signal Descriptions (Continued)

Signal Name

Multiplexed

Signal(s)

Type Description

Queue Status Pins

QS1 QS0 Queue Operation

0 0 None

0 1 First opcode byte fetched from queue

1 0 Queue was initialized

1 1 Subsequent byte fetched from queue

20 Am186™CC Communications Controller Data Sheet

[PCS7]

[PCS6]

[PCS5]

[PCS4

]

PCS3

PCS2

PCS1

PCS0

PIO31

PIO32

PIO2

PIO3

{CLKSEL2}

—

[PIO14]

{USBSEL2}

[PIO13]

{USBSEL1}

O Peripheral Chip Selects 7–0 indicate to the system that an access is in

progress to the corresponding region of the peripheral address block (either I/O

or memory address space). The base address of the peripheral address block is

programmable. PCS7

–PCS0 are three-stated with pullup resistors during bus-

hold or reset conditions.

Unlike the UCS

and LCS chip selects that operate relative to the earlier timing of

the nonmultiplexed A address bus, the PCS

outputs assert with the multiplexed

AD address and data bus timing.

UCS

{ONCE}OUpper Memory Chip Select indicates to the system that a memory access is in

progress to the upper memory block. The base address and size of the upper

memory block are programmable up to 512 Kbytes. UCS

is three-stated with a

weak pullup during bus-hold or reset conditions.

The UCS

can be configured for an 8-bit or 16-bit bus size out of reset. For

additional information, see the {UCSX8

} pin description in Table 31, “Reset

Configuration Pins (Pinstraps),” on page A-10.

After reset, UCS

is active for the 64-Kbyte memory range from F0000h to FFFFFh,

including the reset address of FFFF0h.

DRAM

[CAS1

]

[CAS0]

MCS1

MCS2

O Column Address Strobes 1–0: When either the upper or lower chip select

regions are configured for DRAM, these pins provide the column address strobe

signals to the DRAM. The CAS signals can be used to perform byte writes in a

manner similar to WHB

and WLB, respectively (i.e., [CAS0] corresponds to the

low byte (WLB

) and [CAS1] corresponds to the high byte (WHB)).

[RAS1

][MCS3]

PIO5

O Row Address Strobe 1: When the upper chip select region is configured to

DRAM, this pin provides the row address strobe signal to the upper DRAM bank.

[RAS0]LCS O Row Address Strobe 0: When the lower chip select region is configured to

DRAM, this pin provides the row address strobe signal to the lower DRAM bank.

Table 4. Signal Descriptions (Continued)

Signal Name

Multiplexed

Signal(s)

Type Description

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