
FlexRay Protocol Specification
Version 2.1 Revision A 15-December-2005
Chapter 8: Clock Synchronization
Page 173 of 245
communication cycle. Although the SDL indicates that this computation cannot begin before the
NIT, an implementation may start the computation of this parameter within the dynamic segment or
symbol window as long as the reaction to the computation (update of the CHI and transmission of
the SyncCalcResult and offset calc ready signals) is delayed until the NIT. The calculation must be
complete before the offset correction phase begins.
• Rate (frequency) changes are described by the variable vRateCorrection. vRateCorrection is an
integer number of microticks that are added to the configured number of microticks in a communica-
tion cycle (pMicroPerCycle)
93
. vRateCorrection may be negative. The value of vRateCorrection is
determined by the clock synchronization algorithm and is only computed once per double cycle. The
calculation of vRateCorrection takes place following the static segment in an odd cycle. The calcula-
tion of vRateCorrection is based on the values measured in an even-odd double cycle. Although the
SDL indicates that this computation cannot begin before the NIT, an implementation may start the
computation of this parameter within the dynamic segment or symbol window as long as the
reaction to the computation (update of the CHI and transmission of the SyncCalcResult and rate
calc ready signals) is delayed until the NIT. The calculation must be completed before the next even
cycle begins.
The following data types will be used in the definition of the clock synchronization process:
newtype T_EvenOdd
literals even, odd;
endnewtype;
syntype
T_Deviation = T_Microtick
endsyntype;
Definition 8-2: Formal definition of T_EvenOdd and T_Deviation.
The protocol operation control (POC) process sets the operating mode for the clock synchronization
process (CSP) (Figure 8-4) into one of the following modes:
1. In the STANDBY mode the clock synchronization process is effectively halted.
2. In the NOSYNC mode CSP performs clock synchronization under the assumption that it is not trans-
mitting sync frames (i.e., it does not include its own clock in the clock correction computations).
3. In the SYNC mode CSP performs clock synchronization under the assumption that it is transmitting
sync frames (i.e., it includes its own clock in the clock correction computations).
Definition 8-3 gives the formal definition of the CSP operating modes.
newtype T_CspMode
literals STANDBY, NOSYNC, SYNC;
endnewtype;
newtype T_SyncCalcResult
literals WITHIN_BOUNDS, EXCEEDS_BOUNDS, MISSING_TERM;
endnewtype;
Definition 8-3: Formal definition of T_CspMode and T_SyncCalcResult.
After the POC sets the CSP mode to something other than STANDBY, the CSP waits in the CSP:wait for
startup state until the POC forces the node to a cold start or to integrate into a cluster. The startup
procedure, including its initialization and interaction with other processes, is described in the macro
INTEGRATION CONTROL, which is explained in section 8.4.
Before further explanation of the processes an array is defined (Definition 8-4) which is used to store the
frame IDs of the received sync frames.
93
pMicroPerCycle is the configured number of microticks per communication cycle without correction.