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JC-45-2260.01 JESD400-5 DDR5 SPD Contents Document Release 0.92
SPD BASE CONFIGURATION SECTION April 29, 2020 6
P R O P O S E D
5.0 Parsing the SPD
Some Relevant SPD Bytes for Parsing
SPD Byte(s) Definition
1 SPD revision for this memory module
2 DRAM interface type presented or emulated
3 Memory module interface type
0~125 Base configuration and DRAM parameters
192~445 Module specific parameters
510~511 CRC for bytes 0~509
The system BIOS will acquire information from the SPD in order to properly configure the systems
memory controller. It is assumed the BIOS will parse the SPD data in the order listed below.
Step 1: Parse Byte 2 - Verify the installed DRAM type is supported.
The first step is to verify the validity of the conten
ts of the SPD. Each section of the SPD has a 16-
bit cyclic redundancy check (CRC) in the last two bytes of the section. This value represent the
CRC for the previous bytes in that section of the SPD contents. A BIOS should verify the SPD
contents prior to parsing the contents. The CRC for bytes 0~509 is stored in bytes 510~511.
Step 2: Parse Byte 2 - Verify the installed DRAM type is supported.
The first step in parsing the SPD is to verify that
the DRAM type installed is supported by looking at
DRAM device type byte 2. While it is usually not possible to physically plug in the wrong memory
type, for example a DDR3 module size or key location should prevent insertion into a DDR5
system, there are cases where byte 2 is used to prevent accidental use of an incompatible
memory type.
Step 3: Parse Byte 1 - Verify SPD compatibility. See Section 6 - SPD Revision Progression
The SPD revision byte 1 “encoding” nibble may be
used to force legacy systems to reject newer
modules. This would typically only occur if a critical error were found in SPD encoding that would
require a “fix”. In this case, as in the case of an unsupported DRAM type, system initialization must
be halted immediately.
The SPD revision stored in Byte 1 a
pplies to all information for the module, including base
information and module specific information. Each SPD revision exactly defines how many bytes
are valid in all other SPD blocks. The number of supported bytes (or bits) may increase from one
SPD revision to another within each block as indicated by the “additions” nibble of the SPD
revision. For example, an SPD revision 1.3 has more bytes or bits defined than SPD revision 1.2.
This progression of SPD contents is important for the BIOS to
DIMM compatibility model. An older
system may have a BIOS that only understands SPD revision 1.2 encoding, so if a module is
installed that contains revision 1.3 information, the system can accurately interpret all of the
historical revision 1.2 information retained in the module that is the subset of the revision 1.3
specification. Similarly, if a module with SPD revision 1.1 information is installed, that same BIOS
can interpret all information that was current at the time that SPD 1.1 was defined. Therefore,
BIOSes must maintain a knowledge of the active information for each historical SPD revision in
order to support older modules.
New in DDR5 SPD contents definition is a separate revision by
te for sections of the contents. For