Xilinx Spartan-6 FPGA DDR3开发指南详解

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"Xilinx Spartan-6 FPGA DDR3开发手册" Xilinx Spartan-6 FPGA DDR3开发手册是针对使用Xilinx Spartan-6系列FPGA进行DDR3内存接口设计的专业指南。该手册提供了详尽的指导，旨在帮助工程师们理解和实现高效的DDR3内存控制器，从而在系统设计中充分利用Spartan-6 FPGA的内存接口功能。手册涵盖了多个关键知识点，包括： 1. **DDR3内存技术概述**：DDR3是一种高速、低功耗的动态随机存取存储器（DRAM）标准，其工作原理、速度等级、数据传输速率等特性在手册中得到了详细解释。 2. **Spartan-6 FPGA架构**：手册深入介绍了Spartan-6 FPGA的内存块（BRAM）、分布式内存和I/O资源，以及如何利用这些资源来构建DDR3内存控制器。 3. **内存控制器配置**：包括时序参数设置、预读取（Prefetching）、写入后读取（Write-Read-After-Write, WRAP）模式、突发长度（Burst Length）、列地址交错（Bank Interleaving）等，这些都是优化内存性能的重要因素。 4. **时钟管理**：DDR3内存操作对时钟同步有严格要求，手册会详细讲述如何使用Spartan-6 FPGA的全局时钟网络和时钟缓冲器（DLL, DCM）来满足这些要求。 5. **接口信号定义**：手册详细解析了DDR3接口的信号线，如地址线、数据线、控制线和时钟线，以及它们在FPGA和DDR3内存芯片间的交互方式。 6. **设计流程**：从逻辑设计到硬件实现，手册提供了完整的DDR3内存控制器设计步骤，包括使用Xilinx的VHDL或Verilog HDL进行编码、时序约束设定、综合、布局布线以及仿真验证。 7. **IP核集成**：Xilinx提供预配置的DDR3控制器IP核，手册指导用户如何在Xilinx ISE或Vivado设计套件中集成和配置这些IP核。 8. **故障排查与调试**：手册还包含了一些常见问题及解决方法，帮助开发者诊断并修复设计中的错误。 9. **合规性与限制**：手册强调了Xilinx关于使用和分发文档的政策，包括版权和许可条款，以及使用文档进行设计的风险和责任。 10. **技术支持与更新**：尽管Xilinx不承担技术支持的义务，但手册可能会提示用户如何获取最新的更新和技术支持资源。这份手册是开发基于Spartan-6 FPGA的DDR3内存系统时不可或缺的参考资料，它提供了从理论到实践的全面指导，帮助工程师克服设计挑战，实现高效可靠的内存接口。

Spartan-6 FPGA Memory Controller www.xilinx.com 11

UG388 (v2.3) August 9, 2010

Block Diagram

The single data rate (SDR) user interface to the MCB inside the FPGA can be configured for

one to six ports, with each port consisting of a command interface and a read and/or write

data interface. The two 32-bit bidirectional and four 32-bit unidirectional hardware-based

ports inside the MCB can be grouped to create five different port configurations.

Other major components of the MCB include:

•Arbiter

Determines which port currently has priority for accessing the memory device.

• Controller

Primary control block that converts the simple requests made at the user interface into

the necessary instructions and sequences required to communicate with the memory.

• Datapath

Handles the flow of write and read data between the memory device and the user

logic.

• Physical Interface (PHY)

Converts the controller instructions into the actual timing relationships and DDR

signaling necessary to communicate with the memory device.

• Calibration Logic

Calibrates the PHY for optimal performance and reliability.

X-Ref Target - Figure 1-1

Figure 1-1: Spartan-6 FPGA Memory Controller Block (IP Wrapper View)

UG388_c1_01_050409

32-Bit

Bidirectional

Arbiter

PHY

IOB

Datapath

IP Wrapper

Spartan-6 FPGA

Memory

Controller

Calibration

Logic

DDR

DDR2

DDR3

LPDDR

32-Bit

Bidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

CMD FIFO 0

CMD FIFO 1

CMD FIFO 2

CMD FIFO 3

CMD FIFO 4

CMD FIFO 5

User Logic

Dedicated Routing

I/O Clocking Network

12 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Performance

The dedicated MCB cores in Spartan-6 devices enable significantly higher performance

levels than equivalent IP solutions implemented in the FPGA logic. Because memory

bandwidth is often the bottleneck in overall system performance, the MCB cores were

specifically engineered for users looking to maximize memory performance in a low-cost,

low-power FPGA device.

Each MCB core supports the memory interface data rates and total memory bandwidth

specifications shown in Table 1-1. Peak bandwidth for a single MCB memory interface is

calculated for the three supported interface widths.

Note:

The MCB supports Standard and Extended performance modes depending on the selected

CCINT

operating conditions. Peak data rates shown in Tabl e 1- 1 represent maximum performance

when using the V

CCINT

range in Extended performance mode. Refer to Table 2 (Recommended

Operating Conditions) and the Performance Characteristics section in DS162, Spartan-6 FPGA Data

Sheet: DC and Switching Characteristics for V

CCINT

operating conditions and performance

specifications for Standard and Extended modes.

Table 1-1: Memory Interface Data Rates and Peak Bandwidth for Each MCB

Memory Type

Data Rate:

Mb/s DDR (MHz Clock)

Peak Bandwidth per MCB Interface (Gb/s)

Minimum Maximum

(1)

4-Bit 8-Bit 16-Bit

DDR 167 Mb/s

(2)

(83.3 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

DDR2 250 Mb/s

(2)

(125 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

DDR3 606 Mb/s

(2)

(303 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

LPDDR 60 Mb/s

(2)

(30 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

Notes:

1. The maximum MCB data rate shown does not apply to all speed grades. Refer to DS162, Spartan-6

FPGA Data Sheet: DC and Switching Characteristics, for performance by speed grade. The

-3N speed-grade devices do not support the MCB.

2. The minimum frequency requirement of the MCB is dictated by the minimum frequency specification

for the memory standard. See Memory Standards in Appendix A for links to the relevant JEDEC

specifications.

14 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Supported Memory Configurations

The Spartan-6 FPGA MCB supports a wide range of common memory types,

configurations, and densities, as shown in Table 1-3.

Software and Tool Support

The Spartan-6 FPGA MCB is supported by standard software and tool flows like other soft

and embedded IP blocks offered by Xilinx. For conventional (i.e., non-embedded) FPGA

designs, the MCB can be integrated into a design using the Memory Interface Generator

(MIG) tool, available in the CORE Generator tool.

The MIG tool is used to generate memory interfaces for all Xilinx FPGAs. It produces the

necessary RTL design files, user constraints files (UCFs), and script files for simulation and

implementation of memory solutions offered by Xilinx. The Getting Started chapter in

UG416

, Spartan-6 FPGA Memory Interface Solutions User Guide, contains detailed

step-by-step instructions on how to use the MIG tool to implement memory interfaces

based on the MCB.

For embedded designs (e.g., MicroBlaze™ processor designs), the IP configurator GUI

found in the Xilinx Platform Studio tool within the EDK environment can be used to

specify the memory interface characteristics. In this flow, the MCB serves as the underlying

hardware implementation of the MPMC IP block, available in the EDK library. In addition

to setting up the controller and memory attributes, the tool generates the necessary soft

bridges to the PLB bus, Xilinx Cache Link (XCL), LocalLink (LL), or other specified

interface for connecting EDK peripherals to the resulting memory controller ports.

Table 1-3: Supported Memory Configurations

Memory Density

Width

(# DQ bits)

Memory Type

LPDDR DDR DDR2 DDR3

128 Mb x16 X X

x8 X

x4 X

256 Mb x16 X X X

x8 X X

x4 X X

512Mbx16XXXX

x8 XXX

x4 XXX

1 Gbx16XXXX

x8 XXX

x4 XXX

2 Gb x16 X X

x8 X X

x4 X X

4 Gb

(1)

x16 X

Notes:

1. The MCB supports single-die, 4 Gb memory components (when available from memory suppliers) but

not dual-die, 4 Gb memory components.

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