TC358870XBG HDMI to DSI Bridge芯片详解

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"TC358870XBG寄存器说明书是针对Toshiba Corporation生产的CMOS数字集成电路——一款移动外围设备的详细技术文档。该芯片的主要功能是将高清（高于4Gbps）HDMI流转换为MIPIDSI Tx视频信号，适用于驱动DSI链接显示。作为TC358870XBG的升级版，它不包含标量功能，但能够处理297 MHz的HDMI接收器输入，最高可传输7.2 Gbps的视频流，需要双链路MIPIDSI Tx，每链路1 Gbps数据速率。" TC358870XBG的关键特性包括： 1. HDMI-RX接口：遵循HDMI 1.4b标准，能支持多种视频格式，最高可达4K×2K/30fps，最大24位每像素（无深色支持）。支持的视频格式包括RGB和YCbCr444与422，均为24位色彩深度。 2. 颜色转换：芯片内置4:2:2到4:4:4、4:4:4到4:2:2的转换，以及RGB888到YCbCr（4:4:4/4:2:2）和YCbCr（4:4:4/4:2:2）到RGB888/666的转换。对于RGB666格式，R、G、B各取5位有效数据，其余补零。 3. 最大HDMI时钟速度：297 MHz，确保了高分辨率视频的稳定传输。 4. 音频支持：内部集成音频PLL，提供音频同步处理能力，支持多种音频格式，如I2S、SPDIF等，可以处理多声道音频数据。寄存器说明书将详细阐述如何配置和控制TC358870XBG的各项功能。这通常包括各个寄存器的地址、用途、访问类型和默认值，以及如何通过编程修改这些寄存器来实现特定的功能设置，如视频格式选择、颜色空间转换参数、时钟管理等。此外，可能还会涉及错误处理机制、电源管理、中断控制以及调试工具等信息。在实际应用中，这款芯片通常用于智能手机、平板电脑等移动设备，将应用处理器的HDMI输出端口转换为DSI信号，以便连接到LCD或OLED显示器。通过理解和掌握TC358870XBG的寄存器说明书，工程师可以有效地设计和优化系统级解决方案，确保视频和音频数据的高效、高质量传输。

TC358870XBG

16 2015-02-02

Table of Figures

Figure 1.1 TC358870XBG System Overview .......................................................................................... 21

Figure 2.1 TC358870XBG 80-Pin Layout (Top View).............................................................................. 24

Figure 3.1 Block Diagram of TC358870XBG ........................................................................................... 25

Figure 3.2 Line Splitting for Dual DSI Link ............................................................................................... 28

Figure 3.3 Line Overlap Splitting in Dual DSI Link ................................................................................... 29

Figure 3.4 DSI Command Transmission Timing ...................................................................................... 30

Figure 3.5 DSI Short Command Packet Assembly .................................................................................. 31

Figure 3.6 DSI Long Command Packet Assembly .................................................................................. 32

Figure 3.7 Flow diagram for LPRX data reception using Register interface ........................................... 34

Figure 3.8 CEC reception overview ......................................................................................................... 35

Figure 3.9 CEC noise cancellation example ............................................................................................ 36

Figure 3.10 CEC start bit detection .......................................................................................................... 36

Figure 3.11 waveform error detection ...................................................................................................... 37

Figure 3.12 sampling time example ......................................................................................................... 37

Figure 3.13 CEC transmission example .................................................................................................. 38

Figure 3.14 Transmission starts ............................................................................................................... 38

Figure 3.15 Transmission timing .............................................................................................................. 39

Figure 3.16 Arbitration Error check .......................................................................................................... 39

Figure 3.17 CEC Block diagram............................................................................................................... 40

Figure 3.18 Data input timing of standard format (Sony format); L_ch=H, R_ch=L ................................ 42

Figure 3.19 Data input timing of Left-Justified format; L_ch=H, R_ch=L................................................. 42

Figure 3.20 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H ............................. 43

Figure 3.21 HBR Audio stream over 1 I2S lane and four (4) I2S lanes ................................................... 44

Figure 3.22 I2S N-Channel TDM timing ................................................................................................... 45

Figure 3.23 NEC Configuration of Frame ................................................................................................ 46

Figure 3.24 NEC Bit Description .............................................................................................................. 46

Figure 3.25 NEC Frame Interval (Tf) ....................................................................................................... 46

Figure 3.26 Example of Lead Code min/max values for H and L detection ............................................ 47

Figure 3.27 Register Write Transfer over I

C Bus ................................................................................... 49

Figure 3.28 Random Register Read Transfer over I

C Bus .................................................................... 49

Figure 3.29 Continuous Register Read Transfer over I

C Bus ................................................................ 49

Figure 3.30 I

C Write Transfers Translated to Register Write Accesses ................................................ 50

Figure 3.31 I

C Read Transfers to Register Read Accesses .................................................................. 50

Figure 4.1 Power On Sequence ............................................................................................................... 54

Figure 4.2 Power Down Sequence .......................................................................................................... 55

Figure 6.1 TC358870XBG package (P-VFBGA80-0707-0.65-001) ...................................................... 294

Figure 9.1 D-PHY Signaling Levels .................................................................................................... 299

Figure 9.2 Input Glitch Rejection of Low-Power Receivers ................................................................... 302

Figure 9.3 Data to clock timing reference .............................................................................................. 302

Figure 9.4 I2S/TDM Timing Diagram ..................................................................................................... 303

Figure 10.1 Example of DDC I/F Connection ........................................................................................ 305

Figure 10.2 Connection of REXT resistance ......................................................................................... 306

Figure 10.3 Audio Clock External LPF circuit block diagram ................................................................. 306

Figure 10.4 Recommended power supply circuit with external switch .................................................. 307

Figure 10.5 Recommended power supply circuit with current protection regulator .............................. 308

Figure 10.6 Recommended power supply circuit at VDDIO18 = 3.3V .................................................. 309

TC358870XBG

17 2015-02-02

List of Tables

Table 2.1 TC358870XBG Functional Signal List ..................................................................................... 22

Table 2.2 BGA80 Pin Count Summary .................................................................................................... 24

Table 3.1 HDMI 3D Structure ................................................................................................................... 26

Table 3.2 InfoFrame Data Registers Summary ....................................................................................... 27

Table 4.1 Possible DSITX0/1_PLL parameters ....................................................................................... 53

Table 4.2 Power On Sequence Timing .................................................................................................... 54

Table 4.3 Power Down Sequence Timing................................................................................................ 55

Table 5.1 Global Register Map ................................................................................................................ 56

Table 5.2 CEC Enable Register ............................................................................................................. 136

Table 5.3 CEC Logical Address Register .............................................................................................. 137

Table 5.4 CEC Reset Register ............................................................................................................... 137

Table 5.5 CEC Receive Enable Register ............................................................................................... 138

Table 5.6 CEC Receive Control Register 1 ........................................................................................... 138

Table 5.7 CEC Receive Control Register 2 ........................................................................................... 140

Table 5.8 CEC Receive Control Register 3 ........................................................................................... 141

Table 5.9 CEC Transmit Enable Register .............................................................................................. 142

Table 5.10 CEC Transmit Control Register ........................................................................................... 143

Table 5.11 CEC Receive Interrupt Status Register ............................................................................... 144

Table 5.12 Interrupt Flag Register ......................................................................................................... 144

Table 5.13 CEC Receive Buffer Registers (01-16) ................................................................................ 145

Table 5.14 CEC Transmit Buffer Registers (01-16) ............................................................................... 145

Table 5.15 Interrupt Flag Register ......................................................................................................... 145

Table 5.16 CEC Interrupt Enable Register ............................................................................................ 146

Table 5.17 CEC Interrupt Enable Register ............................................................................................ 146

Table 6.1 Mechanical Dimension ........................................................................................................... 294

Table 11.1 Revision History ................................................................................................................... 310

TC358870XBG

19 2015-02-02

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