PCIe 2.0 CEM规范详解：电气与机械设计

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"PCI Express 2.0 Card Electromechanical Specification" PCI Express（PCIe）是一种高速接口标准，用于连接计算机系统中的外部设备，如显卡、网卡和硬盘等。PCIe 2.0 CEM（Card Electromechanical）测试规范是针对PCI Express 2.0版本的扩展卡的机械和电气设计指南，它是PCI Express Base Specification Revision 2.0的补充。这个规范主要关注在现有的PCI桌面/服务器机械和电气规格上的进化策略，尤其着重于ATX或基于ATX的主板形式因素。 PCI Express 2.0是在2007年4月11日发布的，相对于之前的1.1版本，它增加了对5 GT/s数据速率的支持，这意味着更高的传输速度和更大的带宽，这对于高性能计算和图形处理至关重要。此规范涵盖了PCIe卡的设计、制造和测试要求，确保它们能在各种系统环境中稳定工作，并与现有PCI机械结构兼容。该文档的修订历史显示了技术的迭代过程，从1.0到1.1再到2.0，每个版本都包含了错误修正和工程变更通知（ECNs），以逐步完善和优化标准。1.0a版本包含了工作小组的C1-C7和E1错误，而1.1版本则整合了批准的错误更正和工程变更。 PCI-SIG（Peripheral Component Interconnect Special Interest Group）是负责制定和维护PCI标准的组织，他们明确声明不对使用该文档及其包含的信息可能产生的任何后果承担责任，也不承诺更新其中的信息。有兴趣获取最新版本规范的人士应直接联系PCI-SIG办公室。此外，PCI-SIG提供了会员服务和技术支持的联系方式，包括电子邮件、电话和传真，以便于解答有关该规范或PCI-SIG会员资格的问题。对于技术问题，可以通过techsupp@pcisig.com邮箱进行咨询。 PCI Express 2.0 CEM测试规范是确保PCIe 2.0扩展卡在机械和电气方面符合标准的关键文档，它指导了制造商如何制造出与系统兼容、性能可靠的硬件设备。这一规范的重要性在于它推动了高速数据传输技术的发展，为个人电脑和服务器领域的创新提供了坚实的基础。

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0

Note that the SMBus interface pins are collectively optional for both the add-in card and the system

board. If the optional management features are implemented, SMBCLK and SMBDAT are both

required. Similarly, the JTAG pins are collectively optional. If this test mode is implemented, all the

JTAG pins are required. Refer to the PCI Local Bus Specification, Revision. 3.0, Section 4.3.3 for

additional system requirements related to these signals. 5

2.1. Reference Clock

2.1.1. Low Voltage Swing, Differential Clocks

To reduce jitter and allow for future silicon fabrication process changes, low voltage swing,

differential clocks are being used, as illustrated in Figure 2-1. The nominal single-ended swing for

each clock is 0 to 0.7 V and a nominal frequency of 100 MHz ±300 PPM. The clock has a defined

crossover voltage range and monotonic edges through the input threshold regions as specified in

Chapter 4. 10

period

REFCLK–

REFCLK+

OM14741

Figure 2-1: Differential REFCLK Waveform

The reference clock pair is routed point-to-point to each connector from the system board

according to best-known clock routing rules. The reference clock distribution to all devices must be

matched to within 15 inches on the system board. The transport delay delta between the data and

clock at the Receiver is assumed to be less than 10 ns. The combination of the maximum reference

clock mismatch and the maximum channel length will contribute approximately 7-8 ns and the

remaining time is allocated to the difference in the insertion delays of the Tx and Rx devices. The

routing of each signal in any given clock pair between the clock source and the connector must be

well matched in length (< 0.005 inch) and appropriately spaced away from other non-clock signals

to avoid excessive crosstalk.

The add-in card is not required to use the reference clock on the connector. However, the add-in 20

card is required to maintain the 600-ppm data rate matching specified in Section 4.3.7.1 of the PCI

Express Base Specification, Revision 2.0.

Any terminations required by the clock are to be on the system board. An example termination

topology for a current-mode clock generator is shown in Figure 2-2. EMI emissions will be reduced

if clocks to open sockets are shut down at the clock source. The method for detecting the presence 25

of a card in a slot and controlling the clock gating is platform specific and is not covered in this

specification.

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0

2.1.3. REFCLK AC Specifications

All specifications in Table 2-1 are to be measured using a test configuration as described in Note 11

with a circuit as shown in

Figure 2-9.

Table 2-1: REFCLK DC Specifications and AC Timing Requirements

100 MHz Input

Symbol Parameter

Min Max

Unit Note

Rising Edge

Rate

Rising Edge Rate 0.6 4.0 V/ns 2, 3

Falling Edge

Rate

Falling Edge Rate 0.6 4.0 V/ns 2, 3

VIH Differential Input High Voltage +150 mV 2

VIL Differential Input Low Voltage -150 mV 2

VCROSS Absolute crossing point voltage +250 +550 mV 1,4,5

VCROSS DELTA

Variation of VCROSS over all rising

clock edges

+140 mV 1,4,9

VRB Ring-back Voltage Margin -100 +100 mV 2,12

TSTABLE Time before VRB is allowed 500 ps 2,12

TPERIOD AVG Average Clock Period Accuracy -300 +2800 ppm 2,10,13

TPERIOD ABS

Absolute Period (including Jitter

and Spread Spectrum

modulation)

9.847 10.203 ns 2,6

TCCJITTER Cycle to Cycle jitter 150 ps 2

VMAX Absolute Max input voltage +1.15 V 1,7

VMIN Absolute Min input voltage - 0.3 V 1,8

Duty Cycle Duty Cycle 40 60 % 2

Rise-Fall

Matching

Rising edge rate (REFCLK+) to

falling edge rate (REFCLK-)

matching

20 % 1,14

ZC-DC Clock source DC impedance 40 60

1,11

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus

REFCLK-). The signal must be monotonic through the measurement region for rise and fall time.

The 300 mV measurement window is centered on the differential zero crossing. See

Figure 2-7.

4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+

equals the falling edge of REFCLK-. See

Figure 2-3. 10

5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge

is crossing. Refers to all crossing points for this measurement. See

Figure 2-3.

6. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle

jitter, relative PPM tolerance, and spread spectrum modulation. See

Figure 2-6.

7. Defined as the maximum instantaneous voltage including overshoot. See

Figure 2-3. 15

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0

8. Defined as the minimum instantaneous voltage including undershoot. See

Figure 2-3.

9. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-.

This is the maximum allowed variance in V

CROSS

for any particular system. See Figure 2-4.

10. Refer to Section 4.3.7.1 of the PCI Express Base Specification, Revision 2.0 for information

regarding PPM considerations.

11. System board compliance measurements must use the test load card described in Figure 2-9.

REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must

be used for measurements requiring single ended measurements. Either single ended probes with

math or differential probe can be used for differential measurements. Test load C

= 2 pF.

12. T

STABLE

is the time the differential clock must maintain a minimum ±150 mV differential voltage after 10

rising/falling edges before it is allowed to droop back into the V

±100 mV differential range. See

Figure 2-8.

13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is

1/1,000,000

of 100.000000 MHz exactly or 100 Hz. For 300 PPM then we have an error budget

of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with 15

measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not

employ Spread Spectrum Clocking or that use common clock source. For systems employing

Spread Spectrum Clocking there is an additional 2500 PPM nominal shift in maximum period

resulting from the 0.5% down spread resulting in a maximum average period specification of

+2800 PPM

14. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is

measured using a ±75 mV window centered on the median cross point where REFCLK+ rising

meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be

compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed

20% of the slowest edge rate. See Figure 2-5.

REFCLK–

A-0437

REFCLK+

MAX

= 1.15 V

MIN

= -0.30 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

Figure 2-3: Single-Ended Measurement Points for Absolute Cross Point and Swing

REFCLK–

A-0438

REFCLK+

CROSS DELTA

= 140 mV

Figure 2-4: Single-Ended Measurement Points for Delta Cross Point

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