CYUSB3014：集成USB3.0转换器，ARM核心与高级特性

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本文档介绍的是Cypress半导体公司推出的CYUSB3014芯片，这是一款集成了高性能USB3.0功能的转换器，它具有多项先进的特性，使其在USB3.0设计开发领域具有很高的实用价值。首先，CYUSB3014作为一款USB3.0转换器，支持USB3.0和USB2.0标准，符合USB3.0 1.0规范，能够提供高达5 Gbps的数据传输速率，满足高速传输需求。该芯片具备HS-OTG（High-Speed On-The-Go）功能，兼容USB3.0 On-The-Go补充版本2.0，使得设备可以在主机和外设模式间无缝切换，增强了设备的灵活性。其核心部分是嵌入式ARM926EJ Core处理器，运行速度达到200 MHz，提供了强大的处理能力，内含512 kB的嵌入式静态随机存储器(SRAM)，能满足高效的数据处理和存储需求。此外，CYUSB3014还配备了一个可编程的GPIF II接口，最高工作频率可达100 MHz，支持8/16/32位数据总线和最多16个可配置控制信号，可以连接各种外部设备，如I2C主控制器、I2C发送器、高达4 Mbps的UART通信以及33 MHz SPI主控，为外围设备扩展提供了丰富的接口选项。值得一提的是，该芯片还支持电池充电规范1.1，可以检测并管理外部电源，适配于USB accessory charger adapter (ACA)，这对于移动设备的充电管理和电源管理至关重要。另外，用户可以根据应用选择不同的时钟输入频率，进一步优化系统性能。 CYUSB3014凭借其集成度高、性能强大、兼容性好等特点，对于那些需要在USB3.0环境中设计复杂外围设备或者实现高速数据交换的项目来说，无疑是一个理想的解决方案。无论是嵌入式系统、工业自动化还是消费类电子设备，这款产品都能提供高效且可靠的USB3.0连接能力。开发人员在使用此芯片时，可以充分利用其强大的处理器和灵活的外设接口，简化设计流程，缩短开发周期，提高产品质量。

PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H Page 7 of 38

JTAG Interface

EZ-USB FX3’s JTAG interface provides a standard five-pin

interface for connecting to a JTAG debugger to debug firmware

through the CPU-core's on-chip-debug circuitry.

Industry standard debugging tools for the ARM926EJ-S core can

be used for EZ-USB FX3 application development.

Other Interfaces

EZ-USB FX3 supports the following serial peripherals:

■ UART

■ I

■ SPI

The SPI, UART and I

S interfaces are multiplexed on the Serial

Peripheral port.

The Pin List on page 32 shows details of how these interfaces

are multiplexed.

UART Interface

The UART interface of EZ-USB FX3 supports full duplex

communication. It includes the signals noted in Table 1.

The UART is capable of generating a range of baud rates from

300 bps to 4608 Kbps selectable by the firmware.

C Interface

EZ-USB FX3 has an I

C interface compatible with the I

C Bus

Specification Revision 3. EZ-USB FX3’s I

C interface is capable

of operating as I

C Master only, hence may be used to

communicate with other I

C slave devices. For example,

EZ-USB FX3 may boot from an EEPROM connected to the I

interface, as a selectable boot option.

EZ-USB FX3’s I

C Master Controller also supports Multi-master

mode functionality.

The power supply for the I

C interface is VIO5, which is a

separate power domain from the other serial peripherals. This is

to allow the I

C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The bus frequencies supported by the I

C controller are 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz.

Both SCL and SDA signals of the I

C interface require external

pull-up resistors. The pull-up resistors must be connected to

VIO5.

S Interface

EZ-USB FX3 has an I

S port to support external audio codec

devices. EZ-USB FX3 functions as I

S Master as transmitter

only. The I

S interface consists of four signals: clock line

(I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS),

and master system clock (I2S_MCLK). EZ-USB FX3 can

generate the system clock as an output on I2S_MCLK or accept

an external system clock input on I2S_MCLK.

The sampling frequencies supported by the I

S interface are

32 kHz, 44.1 kHz, and 48 kHz.

SPI Interface

EZ-USB FX3 supports an SPI Master interface on the Serial

Peripherals port.The maximum frequency of operation is

33 MHz.

The SPI controller supports four modes of SPI communication

with Start-Stop clock. The SPI controller is a single master

controller with a single automated SSN control. It supports

transaction sizes from 4-bit to 32 bits long.

Boot Options

EZ-USB FX3 can load boot images from various sources,

selected by the configuration of the PMODE pins. The boot

options for EZ-USB FX3 are listed as follows:

■ Boot from USB

■ Boot from I

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

■ Boot from GPIF II ASync ADMUX mode

■ Boot from GPIF II Sync ADMUX mode

■ Boot from GPIF II ASync SRAM mode

Table 1. UART Interface Signals

Signal Description

TX Output signal

RX Input signal

CTS Flow control

RTS Flow control

Table 2. Booting Options for EZ-USB FX3

PMODE[2:0]

[2]

Boot From

F00 Sync ADMUX (16-bit)

F01 Async ADMUX (16-bit)

F11 USB boot

F0F Async SRAM (16-bit)

F1F I

C, On Failure, USB Boot is Enabled

1FF I

C only

0F1 SPI, On Failure, USB Boot is Enabled

Note

2. F indicates Floating.

[+] Feedback [+] Feedback

PRELIMINARY

CYUSB3014

Document Number 001-52136 Rev. *H Page 8 of 38

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on EZ-USB

FX3. The specific reset sequence and timing requirements are

detailed in Figure 17 and Tabl e 15.

Soft Reset

Soft Reset involves the processor setting the appropriate bits in

the PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset - The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset - This reset is identical to Hard Reset. The

firmware must be reloaded following a Whole Device Reset.

Clocking

EZ-USB FX3 allows either a crystal to be connected between the

XTALIN and XTALOUT pins or an external clock to be connected

at the CLKIN pin.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

EZ-USB FX3 has an on-chip oscillator circuit that uses an

external 19.2 MHz (±100 ppm) crystal (when the crystal option is

used). The FSLC[2:0] pins must be configured appropriately to

select the crystal option/clock frequency option. The configu-

ration options are shown in Ta b le 3.

Clock inputs to EZ-USB FX3 must meet the phase noise and

jitter requirements specified in Table 4.

The input clock frequency is independent of the clock/data rate

of EZ-USB FX3 core or any of the device interfaces (including

P-Port and S-Port). The internal PLL applies the appropriate

clock multiply option depending on the input frequency.

32-kHz Watchdog Timer Clock Input

EZ-USB FX3 includes a watchdog timer. The watchdog timer can

be used to interrupt the ARM926EJ-S core, auto wakeup

EZ-USB FX3 in Standby mode and reset the ARM926EJ-S core.

The watch dog timer runs off a 32 kHz clock. This 32 kHz clock

may optionally be supplied from an external source on a

dedicated pin of EZ-USB FX3.

The watchdog timer can be disabled by firmware.

Requirements for the optional 32 kHZ clock input are listed in

Table 5.

Table 3. Crystal/Clock Frequency Selection

FSLC[2] FSLC[1] FSLC[0] Crystal/ Clock Frequency

0 0 0 19.2 MHz crystal

1 0 0 19.2 MHz input CLK

1 0 1 26 MHz input CLK

1 1 0 38.4 MHz input CLK

1 1 1 52 MHz input CLK

Table 4. Input Clock Specifications for EZ-USB FX3

Parameter Description

Specification

Units

Min Max

Phase noise 100 Hz Offset – –75 dB

1 kHz Offset – –104 dB

10 kHz Offset – –120 dB

100 kHz Offset – –128 dB

1 MHz Offset – –130 dB

Maximum frequency deviation – 150 ppm

Duty cycle 30 70 %

Overshoot – 3 %

Undershoot – –3 %

Rise time/fall time – 3 ns

Table 5. 32 kHz Clock Input Requirements

Parameter Min Max Units

Duty cycle 40 60 %

Frequency deviation – ±200 ppm

Rise time/fall time – 3 ns

[+] Feedback [+] Feedback

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