Microchip KSZ8863MLL-FLL-RLL 数据手册：高级开关功能与配置选项

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KSZ8863MLL-FLL-RLL 数据手册详细介绍了这款高级交换芯片的功能特性。它专为满足工业级网络应用而设计，具备一系列先进的功能，包括： 1. **IEEE 802.1q VLAN 支持**：支持多达16个VLAN组，VLAN ID 可配置，可以进行VLAN标签或去标签操作，具有端口级别的灵活性。 2. **IEEE 802.1p/q 标签处理**：允许在每个端口上进行 IEEE 802.1p 和 802.1q 标签的插入或移除，对入站流量进行精细化控制。 3. **速率限制**：提供可编程的入口和出口速率限制，有助于流量管理，防止广播风暴。 4. **Rapid Spanning Tree Protocol (RSTP)**：支持快速生成树协议，提高网络连通性和可靠性。 5. **Tail Tag 模式**：在 Port 3 中启用，通过在 FCS 前添加一个字节，帮助处理器识别哪个入口端口接收了数据以及其优先级。 6. **Bypass 功能**：当 CPU（通过 Port 3 接口）进入睡眠模式时，自动保持 Port 1 和 Port 2 之间的通信畅通。 7. **自我地址过滤**：保护网络免受恶意流量的干扰，仅允许合法设备接入。 8. **独立 MAC 地址**：为 Port 1 和 Port 2 提供单独的 MAC 地址，增加端口的标识性。 9. **接口兼容性**：支持 RMII 接口，并提供 50MHz 的参考时钟输出，方便与其他硬件设备连接。 10. **IGMP Snooping**：内置 IPv4 IGMP Snooping 功能，用于多播包过滤，优化多播流量的管理。 11. **QoS 支持**：无论是 IPv4 还是 IPv6，都提供了服务质量控制，确保关键业务的优先级。 12. **MAC 过滤**：能够将未知单播包转发到指定端口，增强网络安全性。 13. **全面配置**：通过串行管理接口 (SMI) 对所有内部寄存器进行便捷的访问和配置，便于系统设置和维护。这款交换芯片提供了强大的功能集，适合在需要高效率、可靠性和安全性网络环境中使用，如企业局域网、数据中心或工业自动化系统。其配置灵活且易于管理，有助于简化网络部署和维护工作。

 2017 Microchip Technology Inc. DS00002335B-page 15

KSZ8863MLL/FLL/RLL

FIGURE 3-3: AUTO-NEGOTIATION AND PARALLEL OPERATION

3.1.12 LINKMD

CABLE DIAGNOSTICS

KSZ8863MLL/FLL/RLL supports LinkMD. The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the

cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes

the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault. Inter-

nal circuitry displays the TDR information in a user-readable digital format.

Cable diagnostics are only valid for copper connections and do not support fiber optic operation.

3.1.12.1 Access

LinkMD is initiated through accessing the PHY special control/status registers {26, 42} and the LinkMD result registers

{27, 43} for ports 1 and 2 respectively; and in conjunction with the port registers control 13 for ports 1 and 2 respectively

to disable Auto MDI/MDIX.

Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.

3.1.12.2 Usage

The following is a sample procedure for using LinkMD with registers {42, 43, 45} on port 2:

1. Disable auto MDI/MDI-X by writing a ‘1’ to register 45, bit [2] to enable manual control over the differential pair

used to transmit the LinkMD pulse.

START AUTO-NEGOTIATION

FORCE LINK SETTING

LISTEN FOR 10BASE-T

LINK PULSES

LISTEN FOR 100BASE-TX

IDLES

ATTEMPT AUTO-

NEGOTIATION

LINK MODE SET

BYPASS AUTO-NEGOTIATION

AND SET LINK MODE

LINK MODE SET?

PARALLEL

OPERATION

YES

JOIN FLOW

KSZ8863MLL/FLL/RLL

DS00002335B-page 16  2017 Microchip Technology Inc.

2. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing.

3. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete.

4. Read cable diagnostic test results in register 42, bits [6:5]. The results are as follows:

00 = normal condition (valid test)

01 = open condition detected in cable (valid test)

10 = short condition detected in cable (valid test)

11 = cable diagnostic test failed (invalid test)

The ‘11’ case, invalid test, occurs when KSZ8863MLL/FLL/RLL is unable to shut down the link partner. In this instance,

the test is not run because it is impossible for KSZ8863MLL/FLL/RLL to determine if the detected signal is a reflection

of the signal generated or a signal from another source.

5. Get the distance to fault by concatenating register 42, bit [0] and register 43, bits [7:0]; and multiplying the result

by a constant of 0.4. The distance to the cable fault can be determined by the following formula:

EQUATION 3-1:

Concatenated values of registers 42 and 43 are converted to decimal before multiplying by 0.4.

The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that

varies significantly from the norm.

3.2 Power Management

KSZ8863MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to

ensure low-power dissipation during device idle periods. There are five operation modes under the power management

function, which is controlled by two bits in register 195 (0xC3) and one bit in register 29 (0x1D), 45(0x2D) as shown

below:

• Register 195 bit [1:0] = 00 Normal Operation Mode

• Register 195 bit [1:0] = 01 Energy Detect Mode

• Register 195 bit [1:0] = 10 Soft Power Down Mode

• Register 195 bit [1:0] = 11 Power Saving Mode

• Register 29, 45 bit 3 = 1 Port Based Power Down Mode

Table 3-3 indicates all internal function blocks status under four different power management operation modes.

3.2.1 NORMAL OPERATION MODE

This is the default setting bit [1:0] = 00 in register 195 after the chip power-up or hardware reset. When KSZ8863MLL/

FLL/RLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is

ready for CPU read or write.

TABLE 3-3: INTERNAL FUNCTION BLOCK STATUS

KSZ8863MLL/FLL/RLL

Function Blocks

Power Management Operation Modes

Normal Mode

Power Saving

Mode

Energy Detect

Mode

Soft Power Down

Mode

Internal PLL Clock Enabled Enabled Disabled Disabled

Tx/Rx PHY Enabled

Rx unused block

disabled

Energy detect at Rx Disabled

MAC Enabled Enabled Disabled Disabled

Host Interface Enabled Enabled Disabled Disabled

DDis cetan

to cable fault in meters0.4 Register 26 bit [0] Register 27 bits [7:0]=

 2017 Microchip Technology Inc. DS00002335B-page 17

KSZ8863MLL/FLL/RLL

During the normal operation mode, the host CPU can set the bit [1:0] in register 195 to transit the current normal oper-

ation mode to any one of the other three power management operation modes.

3.2.2 POWER SAVING MODE

The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and bit [1:0] = 11 in

ister values are not changed, and the host interface is ready for CPU read or write. In this mode, it mainly controls the

PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns

off the unused receiver block. Once the activity resumes due to plugging a cable or attempting by the far end to establish

a link, KSZ8863MLL/FLL/RLL can automatically enable the PHY power-up to normal power state from power saving

mode.

During the power saving mode, the host CPU can set bit [1:0] = 0 in register 195 to transit the current power saving

mode to any one of the other three power management operation modes.

3.2.3 ENERGY DETECT MODE

The energy detect mode provides a mechanism to save more power than in the normal operation mode when

KSZ8863MLL/FLL/RLL is not connected to an active link partner. In this mode, the device saves up to 87% of the power.

If the cable is not plugged, KSZ8863MLL/FLL/RLL can automatically enter a low-power state, that is, the energy detect

mode. In this mode, KSZ8863MLL/FLL/RLL keeps transmitting 120 ns width pulses at a rate of 1 pulse/second. Once

the activity resumes due to plugging a cable or attempting by the far end to establish a link, KSZ8863MLL/FLL/RLL can

automatically power up to normal power state in energy detect mode.

Energy detect mode consists of two states: normal power state and low power state. In low power state, KSZ8863MLL/

FLL/RLL reduces the power consumption by disabling all circuitries except the energy detect circuitry of the receiver.

The energy detect mode is entered by setting bit [1:0] = 01 in register 195. When KSZ8863MLL/FLL/RLL is in this mode,

it monitors the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bit [7:0]

Go-Sleep time in register 196, KSZ8863MLL/FLL/RLL goes into a low power state. When KSZ8863MLL/FLL/RLL is in

low power state, it keeps monitoring the cable energy. Once the energy is detected from the cable, KSZ8863MLL/FLL/

RLL enters the normal power state. When KSZ8863MLL/FLL/RLL is in the normal power state, it can transmit or receive

packet from the cable.

It saves about 87% of the power when the MII interface is in PHY mode (register 53 bit 7 = 0), pin SMTXER3/MII_LINK_3

is connected to High, register 195 bit [1:0] = 01, bit 2 = 1(Disable PLL), and no cables are connected.

3.2.4 SOFT POWER DOWN MODE

The soft power down mode is entered by setting bit [1:0] = 10 in register 195. When KSZ8863MLL/FLL/RLL is in this

mode, all PLL clocks are disabled, PHY and MAC are off, and all internal register values are not changed. When the

host set bit [1:0] = 00 in register 195, this device reverts from current soft power down mode to normal operation mode.

3.2.5 PORT-BASED POWER DOWN MODE

In addition, KSZ8863MLL/FLL/RLL features a per-port power down mode. To save power, a PHY port that is not in use

can be powered down via the port control register 29 or 45 bit 3, or the MIIM PHY register. It saves about 15 mA per port.

3.3 MAC and Switch

3.3.1 ADDRESS LOOKUP

The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table

plus switching information.

KSZ8863MLL/FLL/RLL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables,

which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses

it can learn.

3.3.2 LEARNING

The internal lookup engine updates its table with a new entry if the following conditions are met:

• The received packet's Source Address (SA) does not exist in the lookup table.

• The received packet is good; the packet has no receiving errors and is of legal length.

KSZ8863MLL/FLL/RLL

DS00002335B-page 18  2017 Microchip Technology Inc.

The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,

the last entry of the table is deleted to make room for the new entry.

3.3.3 MIGRATION

The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the table

accordingly. Migration happens when the following conditions are met:

• The received packet’s SA is in the table, but the associated source port information is different.

• The received packet is good; the packet has no receiving errors and is of legal length.

The lookup engine updates the existing record in the table with the new source port information.

3.3.4 AGING

The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time

stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record

from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The

aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2].

3.3.5 FORWARDING

KSZ8863MLL/FLL/RLL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 3-4

shows stage one of the forwarding algorithm, where the search engine looks up the VLAN ID, static table, and dynamic

table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by span-

ning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as

shown in Figure 3-5. The packet is sent to PTF2.

FIGURE 3-4: DESTINATION ADDRESS LOOKUP FLOW CHART, STAGE 1

Start

VLAN ID

Valid?

PTF1= NULL

Search Static

Table

Search complete.

Get PTF1 from

Static MAC Table

Dynamic Table

Search complete.

Get PTF1 from

VLAN Table

Search complete.

Get PTF1 from

Dynamic MAC

Table

PTF1

- Search VLAN table

- Ingress VLAN ltering

- Discard NPVID check

YES

FOUND

NOT

FOUND

NOT

FOUND

This search is based on

DA or DA+FID

This search is based on

DA+FID

 2017 Microchip Technology Inc. DS00002335B-page 19

KSZ8863MLL/FLL/RLL

KSZ8863MLL/FLL/RLL does not forward the following packets:

1. Error packets: These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal

size packet errors.

2. IEEE802.3x PAUSE frames: KSZ8863MLL/FLL/RLL intercepts these packets and performs full duplex flow con-

trol accordingly.

3. “Local” packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches

the port from which the packet originated, the packet is defined as local.

3.3.6 SWITCHING ENGINE

KSZ8863MLL/FLL/RLL features a high-performance switching engine to move data to and from the MAC’s packet buf-

fers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.

The switching engine has a 32-kb internal frame buffer. This buffer pool is shared among all three ports. There are a

total of 256 buffers available. Each buffer is sized at 128 bytes.

3.3.7 MAC OPERATION

KSZ8863MLL/FLL/RLL strictly abides by IEEE 802.3 standards to maximize compatibility.

3.3.7.1 Inter Packet Gap (IPG)

If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the

current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.

3.3.7.2 Back-Off Algorithm

KSZ8863MLL/FLL/RLL implements the IEEE 802.3 standard for the binary exponential back-off algorithm and the

optional “aggressive mode” back-off. After 16 collisions, the packet is optionally dropped depending on the switch con-

figuration for register 4 (0x04) bit [3].

FIGURE 3-5: DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2

Spanning Tree

Process

PTF1

IGMP Process

Port Mirror

Process

Port VLAN

Membership

Check

PTF2

- Check receiving port's receive enable bit

- Check destination port's transmit enable bit

- Check whether packets are special (BPDU

or specied)

- RX Mirror

- TX Mirror

- RX or TX Mirror

- RX and TX Mirror

- Applied to MAC #1 and MAC #2

- MAC #3 is reserved for

microprocessor

- IGMP will be forwarded to port 3

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