1700 IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 11, NOVEMBER 2018
Simulation Study of a p-LDMOS With Double
Electron Paths to Enhance Current Capability
Bo Yi , Moufu Kong , and Junji Cheng
Abstract
— In this letter, a p-channel lateral double-
diffused MOSFET (p-LDMOS) with double electron paths
used to enhance the current capability is proposed. The
proposed p-LDMOS has two n-channels that are controlled
by an auto-generated voltage signal (
V
Gn
). The voltage
signal
V
Gn
is generated during the ON and OFF states of the
hole current that flows across an integrated resistor (R
p
)
implemented in the P-base region. Thus, the current capa-
bility of the p-LDMOS can be significantly enhanced by
the introduced electron current. The simulation results
show that the current capability of the proposed p-LDMOS
can be comparable to that of the n-type triple RESURF
technique without any conductivity modulation effect. The
power loss of the proposed p-LDMOS is reduced by approx-
imately 78.6% and 15.6% compared with the triple RESURF
p-LDMOS and n-LDMOS, respectively,at a rated load current
density of 25 µA/µm.
Index Terms
— p-LDMOS, current capability, auto-
controlled, triple RESURF, power loss.
I. INTRODUCTION
P
-CHANNEL Lateral Double-diffused MOSFET
(p-LDMOS) is highly suitable for smart power integrated
circuits (SPIC) [1]–[4], especially for full complementary
high-voltage driver ICs [3], [4]. However, due to the low hole
mobility, the chip area of a p-LDMOS is usually about three
times larger than that of an n-LDMOS with the same current
capability. This also leads to impedance mismatching [2].
To improve the current capability of p-LDMOS, the layout
and field plate optimization are investigated in [5] and [6].
The super-junction solution [7] and the accumulation layer
solution [8], [9] have been proposed to improve the current
capability. However, these approaches are all restricted by
the low hole mobility, making it difficult to compete with
the n-LDMOS. Additionally, some of these approaches even
compromise the dynamic performance due to large gate
charges [9]. To overcome the intrinsic shortcomings of the
p-LDMOS, p-LDMOS devices with electron conductive paths
have been proposed [10], [11]. However, the methods used
in [10] and [11] need several extra controlling circuits and
Manuscript received June 26, 2018; revised August 3, 2018 and
August 31, 2018; accepted September 12, 2018. Date of publication
September 17, 2018; date of current version October 23, 2018. This
work was supported in part by the National Natural Science Foundation
of China under Grant 61804021 and Grant 61504021 and in part by the
Open Foundation of State Key Laboratory of Electronic Thin Films and
Integrated Devices under Grant KFJJ201708. The review of this letter
was arranged by Editor W. T. Ng.
(Corresponding author: Bo Yi.)
The authors are with the State Key Laboratory of Electronic Thin Films
and Integrated Devices, University of Electronic Science and Technology
of China, Chengdu 610054, China (e-mail: yb@uestc.edu.cn).
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2018.2870582
Fig. 1. (a) The proposed p-LDMOS and (b) sectional view along AA
.
components, increasing the design difficulty and cost. In this
letter, a novel p-LDMOS with an auto-controlled n-channel is
proposed and investigated by TCAD simulation. The current
capability of the proposed p-LDMOS can be much larger
than that of the triple RESURF p-LDMOS (TR p-LDMOS)
and is comparable to that of the triple RESURF n-LDMOS
(TR n-LDMOS) without any conductivity modulation effect.
II. S
TRUCTURE AND MECHANISM
OF THE
PROPOSED P-LDMOS
Fig. 1(a) shows the proposed p-LDMOS based on the triple
RESURF technique. The p-LDMOS cell consists of a signal
region in which a signal voltage (V
Gn
) is generated to control
the n-channel and a main current region that is used to conduct
the main load current as shown in Fig. 1(a). Fig. 1(b) shows the
sectional view along AA
in Fig. 1(a). When the p-channel is
turned on, the hole current (current path 1) in the signal region
flows across an integrated resistor (R
P
) in the P-base region
and eventually into electrode D. The voltage signal (V
Gn
) is
auto-generated across R
P
. V
Gn
serves as the gate voltage of
the n-channel to realize the auto-turn-on and auto-turn-off of
the n-channel. As a result, the p-LDMOS utilizes not only the
hole current (shown as current path 1 in Figs. 1(a) and 1(b))
but also two additional electron current paths (shown as current
paths 2 and 3 in the main current region) to conduct the
current. Therefore, the current capability of the p-LDMOS can
be significantly improved.
A deep trench isolation is also formed between the signal
region and the main current region to isolate the P
+
1
region in
the signal region from both the N-epi and N-top regions in the
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