英特尔64G/128G/256G MLC NAND闪存技术规格

5星 · 超过95%的资源需积分: 9 64 浏览量更新于2024-07-31 2 收藏 2.03MB PDF 举报

“INTEL NAND 64G128G256G DATASHEET”是英特尔公司关于其64GB、128GB和256GB NAND闪存芯片的数据手册。该手册详细介绍了这些存储设备的技术规格和特性。在这些NAND闪存芯片中，主要采用了Open NAND Flash Interface (ONFI) 2.2标准，这是一种开放的接口协议，旨在简化NAND闪存与主机系统之间的通信。它们仅支持异步接口，而非同步接口，这意味着数据传输速率可能受到限制，但适用于许多常见的嵌入式和移动应用。这些芯片使用多层单元（MLC）技术，通过在单个单元内存储多个位来提高存储密度。根据容量的不同，设备分别包含4,096个、8,192个或16,384个块。每个块由256个页面组成，每个页面大小为8,640字节，包括8,192字节的实际数据和448字节的附加空间，这可能是用于错误校正代码（ECC）和其他控制信息。在性能方面，随机读取速度最大为50微秒，确保了快速的随机访问能力。而顺序读取速度最小为20纳秒，意味着在连续读取大量数据时有良好的速度表现。页编程（写入）时间平均为1,200微秒，块擦除时间平均为3毫秒，这是NAND闪存常见的写入和擦除操作时间。耐久性方面，这些芯片设计为能承受5,000次编程/擦除（P/E）循环，符合行业标准，适合频繁写入和擦除的应用。数据保留时间符合JEDEC（固态技术协会）的标准，保证在正常工作温度范围内数据的长期稳定性。工作温度范围为0°C至+70°C，属于商业级产品标准。核心电压（VCC）在2.7V到3.6V之间，这是驱动芯片正常工作的电源电压。此外，芯片还提供了硬件级别的功能，如Ready/busy#（R/B#）信号用于检测编程或擦除操作的完成，以及WP#信号实现全设备硬件写保护，防止意外修改数据。这些Intel NAND闪存芯片适用于需要高存储密度、良好读写性能和可靠性的各种电子设备，如移动设备、嵌入式系统和消费类电子产品。

Intel

64M2X NAND Flash Memory

October 2009 Advance Datasheet

Document Number: 999999-001US Intel Confidential 15

Intel

64M2X NAND Flash Memory

6.3 Commands

Commands are written from I/O[7:0] to the command register on the rising edge of

WE# when:

•CE# is LOW,

• ALE is LOW,

•CLE is HIGH,

•RE# is HIGH

Commands are typically ignored by LUNs that are busy; however, the device accepts

the READ STATUS (70h), READ STATUS ENHANCED (78h), and RESET (FFh) commands

when busy.

6.4 Address Input

Addresses are written from I/O[7:0] to the address register on the rising edge of WE#

when:

•CE# is LOW,

•CLE is LOW,

•ALE is HIGH,

•RE# is HIGH

Bits not part of the address space must be LOW. See Table 2, “Array Addressing for 64

Gb LUN” on page 12.

The number of ADDRESS cycles required for each command varies. See Section 7.0,

“Command Definitions” on page 21 to determine addressing requirements.

Addresses are typically ignored by busy LUNs; however, some addresses are accepted

by busy LUNS, such as address cycles that follow the READ STATUS ENHANCED (78h)

command.

6.5 Data Input

Data is written from I/O[7:0] to the data register on the rising edge of WE# when:

•CE# is LOW,

•CLE is LOW,

• ALE is LOW,

•RE# is HIGH

Busy or nonselected LUNS ignore data input unless the LUN is busy with a PAGE CACHE

PROGRAM (80h - 15h) command operation.

Intel

64M2X NAND Flash Memory

Advance Datasheet October 2009

16 Intel Confidential Document Number: 999999-001US

Intel

64M2X NAND Flash Memory

6.6 Data Output

After a READ operation, a LUN can output data if it’s in a ready state. From the selected

LUN, data is output from the cache register to I/O[7:0] on the following edge of RE#

when:

•CE# is LOW,

•CLE is LOW,

• ALE is LOW,

•WE# is HIGH

If a controller uses a

RC timing of 30 ns or longer, the host can latch the data on the

rising edge of RE#. See Figure 81 on page 83 for proper timing. If

RC is less than

30 ns, the host can latch the data on the next falling edge of RE#. See Figure 82 on

page 84 for extended data output (EDO) timing.

A busy LUN will typically ignore requests to output the data from the status register

unless a READ STATUS (70h) or READ STATUS ENHANCED (78h) command has been

issued.

6.7 READs

After a READ command is issued, data is transferred from the memory array to the

data register from the rising edge of WE#. R/B# goes LOW for

R and transitions HIGH

after the transfer is complete. R/B# returns to HIGH at this time. When data is

available in the data register, it is clocked out of the part by RE# going LOW. See

Figure 81, “READ Operation” on page 83 for detailed timing information.

The READ STATUS (70h) command, READ STATUS ENHANCED (78h) command, or the

R/B# signal can be used to determine when the device is ready.

If a controller is using a timing of 30 ns or longer for

RC, use Figure 81 on page 83 for

proper timing. If

RC is less than 30 ns, use Figure 82 on page 84 for extended data

output (EDO) timing.

6.8 Ready/Busy#

The R/B# output provides a hardware method of indicating the completion of

PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for

proper operation. The signal is typically HIGH, and transitions to LOW after the

appropriate command is written to the device. The signal pin’s open-drain driver

enables multiple R/B# outputs to be OR-tied. The READ STATUS (70h) command can

be used in place of R/B#. Typically R/B# would be connected to an interrupt pin on the

system controller (see Figure 11 on page 18).

On the 128 Gb device, R/B# provides a status indication for the 64 Gb section enabled

by CE#, and R/B2# does the same for the 64 Gb section enabled by CE2#.

On the 256 Gb device, R/B1#, R/B2#, R/B3#, and R/B4# each provide an independent

indications for the 64 Gb section enabled by its respective CE#.

剩余91页未读，继续阅读

juzi7908

粉丝: 0
资源: 1

英特尔64G/128G/256G MLC NAND闪存技术规格

海力士NANDFlash选型.pdf

Micron推出新型34纳米高密度NAND产品降低芯片尺寸

美光nandflash datasheet

镁光FLASH DATA SHEET 128G

NandFlash datasheet

nand flash datasheet

SanDisK 24nm 64G eX3 (8LC) Data Sheet

MICRON 256Gb L74A NAND FLASH DATASHEET

镁光NAND Flash Memory Datasheet

各种 nand flash memory datasheet samsung toshiba intel hynix

最新资源