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MSP430FE427, MSP430FE425, MSP430FE423
SLAS396D –JULY 2003–REVISED NOVEMBER 2016
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Specifications Copyright © 2003–2016, Texas Instruments Incorporated
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
5.5 Thermal Resistance Characteristics, PM Package (LQFP64)
PARAMETER VALUE UNIT
Rθ
JA
Junction-to-ambient thermal resistance, still air
(1)
55.7 °C/W
Rθ
JC(TOP)
Junction-to-case (top) thermal resistance
(2)
16.7 °C/W
Rθ
JB
Junction-to-board thermal resistance
(3)
27.1 °C/W
Ψ
JB
Junction-to-board thermal characterization parameter 26.8 °C/W
Ψ
JT
Junction-to-top thermal characterization parameter 0.8 °C/W
5.6 Schmitt-Trigger Inputs − Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS,
TDI/TCLK,TDO/TDI)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER V
CC
MIN MAX UNIT
V
IT+
Positive-going input threshold voltage 3 V 1.5 1.98 V
V
IT-
Negative-going input threshold voltage 3 V 0.9 1.3 V
V
hys
Input voltage hysteresis (V
IT+
- V
IT-
) 3 V 0.45 1 V
(1) The external signal sets the interrupt flag every time the minimum t
(int)
parameters are met. It may be set even with trigger signals
shorter than t
(int)
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
is measured in MCLK cycles.
5.7 Inputs P1.x, P2.x, TAx
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
t
(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag
(1)
3 V
1.5 cycle
50 ns
t
(cap)
Timer_A capture timing TAx 3 V 50 ns
f
(TAext)
Timer_A clock frequency externally
applied to pin
TAxCLK, INCLK t
(H)
= t
(L)
3 V 10 MHz
f
(TAint)
Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz
(1) The leakage current is measured with V
SS
or V
CC
applied to the corresponding pins, unless otherwise noted.
(2) The port pin must be selected as input.
5.8 Leakage Current − Ports (P1 and P2)
(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
lkg(P1.x)
Leakage current, Port P1.x Port 1: V
(P1.x)
(2)
3 V ±50 nA
I
lkg(P2.x)
Leakage current, Port P2.x Port 2: V
(P2.x)
(2)
3 V ±50 nA