EFM32TGTinyGecko微控制器参考手册：超低功耗创新

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"EFM32TG参考手册是关于'TinyGecko'系列微控制器的低功耗ARM寄存器规格书，主要介绍了该系列微控制器的特性、性能以及典型应用。" EFM32TG系列微控制器是全球最节能的微控制器之一，由32位ARM Cortex-M3处理器驱动，工作频率高达32MHz。这一系列设备提供了高达32KB的闪存和4KB的RAM内存，特别适合需要高效能和低功耗的嵌入式应用。在能源效率方面，EFM32TG微控制器拥有自主且节能的外围设备，能够实现超低功耗的能源模式，可在运行模式下以160µA/MHz的电流运行，而睡眠模式下，即使带有实时时钟运行、Brown-out保护以及完整的RAM和寄存器保留功能，功耗也仅为900nA。快速唤醒时间仅为2µs，确保了高效能和响应速度。 EFM32TG的低能量消耗使其在8位、16位和32位解决方案中脱颖而出。其特点包括高度集成的芯片和模拟组件，以及工业标准32位ARM Cortex-M3处理器的性能。这使得EFM32TG系列微控制器不仅适用于传统微控制器的应用，还能够在需要高度节能特性的领域展现其优势。在典型应用方面，EFM32TG微控制器可能被用于： 1. **物联网(IoT)**：由于其低功耗特性，EFM32TG非常适合无线传感器网络、远程监控和智能设备等物联网应用。 2. **可穿戴设备**：在智能手表、健康监测器等设备中，需要长时间运行且对电池寿命有严格要求的场合，EFM32TG能提供理想的解决方案。 3. **能源管理**：在能源采集系统或智能电网中，其高效的电源管理和超低待机功耗是关键。 4. **环境监测**：在遥感监测、气候研究等领域，微控制器需要在低功耗下长时间运行。 5. **家用电器和消费电子**：在智能家电和便携式电子设备中，EFM32TG可以优化能耗，延长产品使用寿命。 6. **汽车电子**：在汽车领域的安全和舒适系统中，其快速唤醒时间和低功耗特性非常有用。 EFM32TG参考手册详细阐述了这些特性，为开发者提供了全面的技术指导，包括硬件接口、外设操作、软件开发以及系统级的能源管理策略，帮助设计人员充分利用这些微控制器的优势，实现创新的低功耗系统设计。

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Table 5.1. Memory System Core Peripherals

Core peripherals

Address range Peripheral

0x400E0400 – 0x41FFFFFF Reserved

0x400E0000 – 0x400E03FF AES

0x400CC400 – 0x400FFFFF Reserved

0x400CC000 – 0x400CC3FF PRS

0x400CA400 – 0x400CBFFF Reserved

0x400CA000 – 0x400CA3FF RMU

0x400C8400 – 0x400C9FFF Reserved

0x400C8000 – 0x400C83FF CMU

0x400C6400 – 0x400C7FFF Reserved

0x400C6000 – 0x400C63FF EMU

0x400C4000 – 0x400C5FFF Reserved

0x400C2000 – 0x400C3FFF DMA

0x400C0400 – 0x400C1FFF Reserved

0x400C0000 – 0x400C03FF MSC

Table 5.2. Memory System Low Energy Peripherals

Low energy peripherals

Address range Peripheral

0x4008A400 – 0x400BFFFF Reserved

0x4008C000 – 0x4008C3FF LESENSE

0x4008A000 – 0x4008A3FF LCD

0x40088400 – 0x40089FFF Reserved

0x40088000 – 0x400883FF WDOG

0x40086C00 – 0x40087FFF Reserved

0x40086000 – 0x400863FF PCNT0

0x40084800 – 0x40085FFF Reserved

0x40084000 – 0x400843FF LEUART0

0x40082400 – 0x40083FFF Reserved

0x40082000 – 0x400823FF LETIMER0

0x40080400 – 0x40081FFF Reserved

0x40080000 – 0x400803FF RTC

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The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any

wait-states. However, the slaves may insert wait-states depending on their internal throughput and the

clock frequency.

The Cortex-M3 and the DMA Controller, and the peripherals (not peripherals in the low frequency clock

domain) run on clocks which can be prescaled separately. When accessing a peripheral which runs on

a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition

to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than the HFCORECLK

cycles

= 2 + N

slave cycles

(5.3)

where N

slave cycles

is the wait cycles introduced by the slave.

When accessing a peripheral which runs on a slower clock than the HFCORECLK, wait cycles are

introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per

access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than the CPU

cycles

= (2 + N

slave cycles

) x f

HFCORECLK

HFPERCLK

(5.4)

where N

slave cycles

is the wait cycles introduced by the slave.

Clocks and prescaling are described in more detail in Chapter 11 (p. 96) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers)

5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system

is powered off, i.e. in energy modes EM2 and in some cases also EM3. This enables the peripherals to

perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are:

• Liquid Crystal Display driver - LCD

• Low Energy Timer - LETIMER

• Low Energy UART - LEUART

• Pulse Counter - PCNT

• Real Time Counter - RTC

• Watchdog - WDOG

• Low Energy Sensor Interface - LESENSE

All Low Energy Peripherals are memory mapped, with standardized data synchronization support.

Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are

some constraints on how register accesses are performed, as described in the following sections. The

constraints are however standardized across all Low Energy Peripherals.

5.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into

the Low Energy clock domain to maintain data consistency and predictable operation. There are two

different synchronization mechanisms on the Tiny Gecko, immediate synchronization, and delayed

synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and

results in an immediate update of the target registers. Delayed synchronization is used for the remaining

Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges of the

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clock on the Low Energy Peripheral being accessed. Registers requiring synchronization are marked

"Asynchronous in their description header.

Note

On the Gecko series of devices, all LE peripherals are subject to delayed synchronization.

5.3.1.1.1 Delayed synchronization

After writing data to a register which value is to be synchronized into the Low Energy Peripheral using

delayed synchronization, a corresponding busy flag in the <module_name>_SYNCBUSY register (e.g.

LCD_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon

completion.

Note

Subsequent writes to the same register before the corresponding busy flag is cleared is not

supported. Write before the busy flag is cleared may result in undefined behavior.

In general the SYNCBUSY register only needs to be observed if there is a risk of multiple

write access to a register (which must be prevented). It is not required to wait until the

relevant flag in the SYNCBUSY register is cleared after writing a register. E.g can EM2 be

entered directly after writing a register.

See Figure 5.3 (p. 19) for an overview of the writing mechanism operation.

Figure 5.3. Write operation to Low Energy Peripherals

Synchronizer 0

Synchronizer 1

Synchronizer n

Write[0:n]

Syncbusy Register 0

Syncbusy Register 1

Syncbusy Register n

Set 0

Set 1

Set n

Freeze

Synchronization Done

Clear 0

Clear 1

Clear n

Core Clock

Low Frequency Clock Low Frequency Clock

Core Clock Domain Low Frequency Clock Dom ain

5.3.1.1.2 Immediate synchronization

In contrast to the peripherals with delayed synchronization, peripherals with immediate synchronization

don't experience a delay from a value is written to it takes effect in the peripheral. They are updated

immediately on the peripheral write access. If such a write is done close to an edge on the clock of

the peripheral, the write is delayed to after the clock edge. This will introduce wait-states on peripheral

access.

On peripherals with delayed synchronization, the SYNCBUSY registers are still present. These have two

purposes: Commands written to a peripheral with immediate synchronization are not executed before the

first peripheral clock after the write. In this period, the SYNCBUSY flag for the command register is set,

indicating that the command has not yet been performed. The second reason is backwards compatibility.

To maintain compatibility with the Gecko series, the rest of the SYNCBUSY registers are also present,

but these are always 0, indicating that register writes are always safe.

Note

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If compatibility with the Gecko series is a requirement for a given application, the rules that

apply to delayed synchronization with respect to SYNCBUSY should also be followed for

the peripherals that support immediate synchronization.

5.3.1.2 Reading

When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates

in the Low Energy clock domain or core clock domain. Registers which are updated/ maintained by the

Low Energy Peripheral are read directly from the Low Energy clock domain. Registers which originate in

the core clock domain, are read from the core clock domain. See Figure 5.4 (p. 20) for an overview

of the reading operation.

Note

Writing a register and then immediately reading the new value of the register may give the

impression that the write operation is complete. This may not be the case. Please refer

to the SYNCBUSY register for correct status of the write operation to the Low Energy

Peripheral.

Figure 5.4. Read operation form Low Energy Peripherals

Synchronizer 0

Synchronizer 1

Synchronizer n

Freeze

Core Clock

Low Frequency Clock Low Frequency Clock

Core Clock Domain Low Frequency Clock Domain

Low Energy

Peripheral

Main

Function

HW Status Register 0

HW Status Register 1

HW Status Register m

Read

Synchronizer

Read Data

5.3.2 FREEZE register

In Low Energy Peripheral with delayed synchronization there is a <module_name>_FREEZE register

(e.g. RTC_FREEZE). The register contains a bit named REGFREEZE. If precise control of the

synchronization process is required, this bit may be utilized. When REGFREEZE is set, the

synchronization process is halted allowing the software to write multiple Low Energy registers before

starting the synchronization process, thus providing precise control of the module update process. The

synchronization process is started by clearing the REGFREEZE bit.

Note

The FREEZE register is also present on peripherals with immediate synchronization, but

there it has no effect

5.4 Flash

The Flash retains data in any state and typically stores the application code, special user data and

security information. The Flash memory is typically programmed through the debug interface, but can

also be erased and written to from software.

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EFM32TGTinyGecko微控制器参考手册：超低功耗创新

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