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首页飞思卡尔KL16 32位低功耗MCU参考手册:Cortex-M0+核心与特性详解
本资源是飞思卡尔半导体(Freescale)针对其32位低功耗Kinetis KL16系列芯片的参考手册,KL16系列包括多种型号如MKL16Z256VLH4、MKL16Z32VFM4等,核心处理器基于Cortex-M0+,工作频率高达48MHz。手册旨在为用户提供详尽的技术指南,适用于硬件开发者和系统设计人员。
在文档的第1章"关于此文档"中,作者概述了手册的目的,即帮助读者理解KL16系列的特点、应用范围以及文档的结构和约定。1.1.1节明确了手册的主要目标,即提供设计和调试KL16芯片所需的详细信息,包括引脚配置、功能模块介绍等。1.1.2部分指出了读者群体,主要包括硬件工程师、嵌入式软件开发人员和系统集成商。
第二章"介绍"深入探讨了Kinetis L系列整体框架,以及KL16子系列在其中的位置。KL16被归类为模块化的系统,具备ARM Cortex-M0+核心模块、系统模块、内存及接口、时钟管理、安全与完整性模块以及模拟和定时器模块。这些模块协同工作,确保芯片在低功耗和高性能之间取得平衡。
2.4.1节详细介绍了ARM Cortex-M0+核心模块,这是KL16芯片的核心部分,提供了强大的处理能力和低功耗特性,适合于电池供电的物联网设备和微控制器应用。系统模块则涉及外围接口控制、中断管理和电源管理等功能,使得芯片能够适应各种复杂的应用场景。
内存和接口模块(2.4.3)涵盖了片内RAM、闪存、以及不同类型的外设接口,如UART、SPI、I2C等,以支持丰富的通信和数据存储需求。时钟管理模块(2.4.5)对于保证精确的时间同步和系统运行效率至关重要,而安全和完整性模块则关注数据保护和系统安全。
模拟模块(2.4.6)可能包括模拟输入/输出、ADC和DAC,有助于实现传感器数据采集和模拟信号处理。最后,定时器模块(2.4.7)为精确的定时、计数和脉冲宽度调制(PWM)控制提供了基础,对于工业自动化、电机控制等应用至关重要。
这份KL16Sub-Family Reference Manual是理解和使用飞思卡尔KL16芯片设计和编程的必备参考资料,提供了全面的硬件和软件设计指导,确保用户能够充分利用这款高性能低功耗芯片的潜力。
Section number Title Page
24.4 Functional Description..................................................................................................................................................388
24.4.1 MCG mode state diagram............................................................................................................................388
24.4.2 Low Power Bit Usage..................................................................................................................................393
24.4.3 MCG Internal Reference Clocks..................................................................................................................393
24.4.4 External Reference Clock............................................................................................................................394
24.4.5 MCG Fixed frequency clock .......................................................................................................................394
24.4.6 MCG PLL clock ..........................................................................................................................................395
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................395
24.5 Initialization / Application information........................................................................................................................396
24.5.1 MCG module initialization sequence...........................................................................................................396
24.5.2 Using a 32.768 kHz reference......................................................................................................................398
24.5.3 MCG mode switching..................................................................................................................................399
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................409
25.2 Features and Modes......................................................................................................................................................409
25.3 Block Diagram..............................................................................................................................................................410
25.4 OSC Signal Descriptions..............................................................................................................................................410
25.5 External Crystal / Resonator Connections....................................................................................................................411
25.6 External Clock Connections.........................................................................................................................................412
25.7 Memory Map/Register Definitions...............................................................................................................................413
25.7.1 OSC Memory Map/Register Definition.......................................................................................................413
25.8 Functional Description..................................................................................................................................................414
25.8.1 OSC Module States......................................................................................................................................414
25.8.2 OSC Module Modes.....................................................................................................................................416
25.8.3 Counter.........................................................................................................................................................418
25.8.4 Reference Clock Pin Requirements.............................................................................................................418
25.9 Reset..............................................................................................................................................................................418
25.10 Low Power Modes Operation.......................................................................................................................................419
KL16 Sub-Family Reference Manual, Rev. 2, December 2012
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Preliminary
Freescale Semiconductor, Inc.
Freescale Confidential Proprietary - Non-Disclosure Agreement required
Section number Title Page
25.11 Interrupts.......................................................................................................................................................................419
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................421
26.1.1 Overview......................................................................................................................................................421
26.1.2 Features........................................................................................................................................................421
26.2 Modes of operation.......................................................................................................................................................422
26.3 External signal description............................................................................................................................................422
26.4 Memory map and register descriptions.........................................................................................................................422
26.5 Functional description...................................................................................................................................................422
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................425
27.1.1 Features........................................................................................................................................................426
27.1.2 Block Diagram.............................................................................................................................................426
27.1.3 Glossary.......................................................................................................................................................427
27.2 External Signal Description..........................................................................................................................................428
27.3 Memory Map and Registers..........................................................................................................................................428
27.3.1 Flash Configuration Field Description.........................................................................................................428
27.3.2 Program Flash IFR Map...............................................................................................................................429
27.3.3 Register Descriptions...................................................................................................................................430
27.4 Functional Description..................................................................................................................................................438
27.4.1 Flash Protection............................................................................................................................................439
27.4.2 Interrupts......................................................................................................................................................439
27.4.3 Flash Operation in Low-Power Modes........................................................................................................440
27.4.4 Functional Modes of Operation...................................................................................................................440
27.4.5 Flash Reads and Ignored Writes..................................................................................................................440
27.4.6 Read While Write (RWW)...........................................................................................................................441
27.4.7 Flash Program and Erase..............................................................................................................................441
KL16 Sub-Family Reference Manual, Rev. 2, December 2012
Freescale Semiconductor, Inc.
Preliminary
17
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Section number Title Page
27.4.8 Flash Command Operations.........................................................................................................................441
27.4.9 Margin Read Commands.............................................................................................................................446
27.4.10 Flash Command Description........................................................................................................................447
27.4.11 Security........................................................................................................................................................460
27.4.12 Reset Sequence............................................................................................................................................462
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................463
28.1.1 Features........................................................................................................................................................463
28.1.2 Block diagram..............................................................................................................................................464
28.2 ADC Signal Descriptions..............................................................................................................................................465
28.2.1 Analog Power (VDDA)...............................................................................................................................466
28.2.2 Analog Ground (VSSA)...............................................................................................................................466
28.2.3 Voltage Reference Select.............................................................................................................................466
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................467
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................467
28.3 Register definition.........................................................................................................................................................467
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................468
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................471
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................473
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................474
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................475
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................476
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................478
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................480
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................480
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................481
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................481
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................482
KL16 Sub-Family Reference Manual, Rev. 2, December 2012
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Preliminary
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Freescale Confidential Proprietary - Non-Disclosure Agreement required
Section number Title Page
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................482
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................483
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................483
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................484
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................484
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................485
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................485
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................486
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................486
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................487
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................487
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................488
28.4 Functional description...................................................................................................................................................488
28.4.1 Clock select and divide control....................................................................................................................489
28.4.2 Voltage reference selection..........................................................................................................................489
28.4.3 Hardware trigger and channel selects..........................................................................................................490
28.4.4 Conversion control.......................................................................................................................................491
28.4.5 Automatic compare function........................................................................................................................499
28.4.6 Calibration function.....................................................................................................................................500
28.4.7 User-defined offset function........................................................................................................................501
28.4.8 Temperature sensor......................................................................................................................................503
28.4.9 MCU wait mode operation...........................................................................................................................503
28.4.10 MCU Normal Stop mode operation.............................................................................................................504
28.4.11 MCU Low-Power Stop mode operation......................................................................................................505
KL16 Sub-Family Reference Manual, Rev. 2, December 2012
Freescale Semiconductor, Inc.
Preliminary
19
Freescale Confidential Proprietary - Non-Disclosure Agreement required
Section number Title Page
28.5 Initialization information..............................................................................................................................................505
28.5.1 ADC module initialization example............................................................................................................505
28.6 Application information................................................................................................................................................507
28.6.1 External pins and routing.............................................................................................................................507
28.6.2 Sources of error............................................................................................................................................509
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................515
29.2 CMP features................................................................................................................................................................515
29.3 6-bit DAC key features.................................................................................................................................................516
29.4 ANMUX key features...................................................................................................................................................517
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................517
29.6 CMP block diagram......................................................................................................................................................518
29.7 Memory map/register definitions..................................................................................................................................520
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................520
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................521
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................523
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................523
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................524
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................525
29.8 Functional description...................................................................................................................................................526
29.8.1 CMP functional modes.................................................................................................................................526
29.8.2 Power modes................................................................................................................................................535
29.8.3 Startup and operation...................................................................................................................................536
29.8.4 Low-pass filter.............................................................................................................................................537
29.9 CMP interrupts..............................................................................................................................................................539
29.10 DMA support................................................................................................................................................................539
29.11 CMP Asyncrhonous DMA support...............................................................................................................................540
29.12 Digital-to-analog converter...........................................................................................................................................540
KL16 Sub-Family Reference Manual, Rev. 2, December 2012
20
Preliminary
Freescale Semiconductor, Inc.
Freescale Confidential Proprietary - Non-Disclosure Agreement required
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