SN75DP119
SLLSE12A –NOVEMBER 2009–REVISED JULY 2014
www.ti.com
7.4 Thermal Information
RGY RHH
THERMAL METRIC
(1)
UNIT
14 PINS 36 PINS
R
θJA
Junction-to-ambient thermal resistance 45 34
R
θJC(top)
Junction-to-case (top) thermal resistance 20 20
R
θJB
Junction-to-board thermal resistance 16 17
°C/W
ψ
JT
Junction-to-top characterization parameter n/a n/a
ψ
JB
Junction-to-board characterization parameter n/a n/a
R
θJC(bot)
Junction-to-case (bottom) thermal resistance 12 12
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
CCDP1max
Supply current 1 DP lane selected WorstCase: 16.2 21.3 mA
EN = V
CC
/2 (1-lane) or V
CC
(2-lane selected);
2.7Gbps PRBS; V
ID
= 400 mV
PP
; V
OD
= 300 mVpp,
8.5 dB pre-emp (PRE_CTL=V
CC
; V
O
D_CTL=GND);
I
CCDP2max
Supply current 2 DP lanes selected 31.7 41.4 mA
EQ_CTL = V
CC
(6 dB); V
CC
= 3.3 V (for typ) and
V
CC
= 3.6 V (for max),
(1)
I
CCDP3max
Supply current 1 DP lane selected EN = V
CC
/2 (1-lane) or VCC (2-lane selected); 12.9 17.6 mA
2.7Gbps PRBS; V
ID
= 400 mV
PP
; V
OD
= 300 mV
PP
,
0 dB pre-emp (PRE_CTL = GND); VOD_CTL = VCC/2);
I
CCDP4max
Supply current 2 DP lanes selected 24.9 34.1 mA
EQ_CTL=GND (0 dB); V
CC
= 3.3 V (for typ) and
V
CC
= 3.6 V (for max),
I
CCDP1typ
Supply current 1 DP lane selected EN = V
CC
/2 (1-lane) or V
CC
(2-lane selected); 14.5 mA
2.7Gbps PRBS; IN/OUT; V
ID
= 600 mV
PP
; (PRE_CTL=GND);
I
CCDP2typ
Supply current 2 DP lanes selected 28.2 mA
VOD_CTL = V
CC
); V
CC
= 3.3 V, EQ_CTL = GND (no EQ)
(2)
I
CCDP3typ
Supply current 1 DP lane selected EN = V
CC
/2 (1-lane) or V
CC
(2-lane selected); 14.5 mA
2.7Gbps PRBS; no pre-emp; IN/OUT; V
ID
= 800 mV
PP
;
(PRE_CTL= VOD_CTL = V
CC
); V
CC
= 3.3 V, EQ_CT L =
I
CCDP4typ
Supply current 2 DP lanes selected 28.2 mA
GND (no EQ)
(3)
IPWRDN Shutdown current (PWRDN mode) EN = GND; 25 100 µA
3-LEVEL CONTROL PINS (EN, VOD_CTL, PRE_CTL, EQ_CTL)
I
L
Low-level input current V
I
= 0.5 V; V
CC
= 3.6 V –30 30 µA
I
H
High-level input current V
I
= V
CC
– 0.5 V; Vcc = 3.6V –30 30 µA
I
M
Mid-level input current V
I
= V
CC
/2 – 0.3V and V
I
= V
CC
/2 + 0.3 V; V
CC
= 3.6 V –30 30 µA
R
bias
Input bias resistance See Figure 6 105 125 145 kΩ
R
ESD
input series resistance to biasing network See Figure 6 2 2.4 kΩ
(1) This current consumption also applies to VOD = 400mV with 5.5 dB pre-emphasis or VOD = 600mV output swing and 2dB pre-
emphasis
(2) This current consumption also applies to VOD = 300mV with 2 dB pre-emphasis
(3) This current consumption also applies to VOD = 300mV with 6dB pre-emphasis or VOD = 400mV output swing and 3.5dB pre-emphasis
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