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Exynos4412处理器用户手册
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更新于2024-07-18
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"三星4412用户手册是针对Exynos 4412 RISC微处理器的技术手册,由三星电子于2012年发布。手册提供了该处理器的详细信息,但三星保留随时更新信息的权利,且不承担任何可能错误或遗漏的责任。此手册本身并不授予与三星或第三方产品相关的任何知识产权许可。三星不对产品的特定用途适用性提供任何保证,也不承担由此产生的应用或使用责任。用户需自行负责其产品和应用设计。"
详细说明:
Exynos 4412是由三星电子开发的一款高性能RISC(Reduced Instruction Set Computer)微处理器,该处理器主要应用于智能手机和平板电脑等移动设备。RISC架构以其高效的指令执行和较低的功耗而著名。Exynos 4412采用的是ARM Cortex-A9四核架构,旨在提供强大的处理能力和高效率,支持多任务处理和高级图形处理。
手册中可能会涵盖以下知识点:
1. **处理器架构**:Exynos 4412的Cortex-A9核心设计,包括每个核心的时钟速度、缓存配置(L1和L2缓存),以及多核间的协作机制(如big.LITTLE架构的早期版本)。
2. **集成GPU**:通常,Exynos 4412会集成Mali-400 MP4 GPU,用于处理图形密集型任务,如游戏和高清视频播放。
3. **内存接口**:处理器与内存的交互方式,如LPDDR2或LPDDR3内存规格,以及内存带宽对性能的影响。
4. **电源管理**:如何通过硬件和软件策略实现高效能与低功耗的平衡,包括动态电压和频率调整(DVFS)。
5. **外设接口**:I/O接口如USB、HDMI、蓝牙、Wi-Fi等,以及它们如何与处理器通信。
6. **系统级芯片(SoC)**:Exynos 4412作为SoC的组成部分,还可能包含其他组件,如ISP(图像信号处理器)和调制解调器,用于蜂窝网络连接。
7. **开发和调试工具**:可能介绍如何使用IDE、调试器和其他工具来开发和优化在Exynos 4412上运行的应用程序。
8. **安全特性**:可能包括安全岛、加密引擎等,用于保护数据安全。
9. **应用示例**:提供针对不同应用场景的代码示例,帮助开发者理解和利用处理器特性。
10. **故障排查**:手册可能提供常见问题和解决方法,以帮助用户和开发者处理可能出现的问题。
请注意,由于手册强调了不提供任何知识产权许可,这意味着使用Exynos 4412设计产品时,必须确保遵循三星和第三方的知识产权规定,避免侵权行为。同时,三星明确表示不承担产品应用或使用导致的任何损害责任,用户应自行负责产品的设计和应用。
35.8 IO Description .................................................................................................................................... 35-19
35.9 Register Description ........................................................................................................................... 35-20
35.9.1 Register Map Summary .............................................................................................................. 35-20
36 IIS-BUS INTERFACE ................................................................................. 36-1
36.1 Overview .............................................................................................................................................. 36-1
36.2 Features ............................................................................................................................................... 36-1
36.3 Block Diagram ...................................................................................................................................... 36-2
36.4 Functional Description ......................................................................................................................... 36-3
36.4.1 Master/Slave Mode ....................................................................................................................... 36-3
36.4.2 DMA Transfer ............................................................................................................................... 36-4
36.4.3 Audio Serial Data Format ............................................................................................................. 36-5
36.4.4 PCM Word Length and BFS Divider ............................................................................................. 36-8
36.4.5 BFS Divider and RFS Divider ....................................................................................................... 36-8
36.4.6 RFS Divider and Root Clock ......................................................................................................... 36-8
36.5 Programming Guide ............................................................................................................................. 36-9
36.5.1 Initialization ................................................................................................................................... 36-9
36.5.2 Play Mode (Tx Mode) with DMA ................................................................................................... 36-9
36.5.3 Recording Mode (Rx Mode) with DMA ......................................................................................... 36-9
36.5.4 Example Code ............................................................................................................................ 36-10
36.6 I/O Description ................................................................................................................................... 36-16
36.7 Register Description ........................................................................................................................... 36-17
36.7.1 Register Map Summary .............................................................................................................. 36-17
37 AC97 CONTROLLER ................................................................................ 37-1
37.1 Overview .............................................................................................................................................. 37-1
37.2 Features ............................................................................................................................................... 37-1
37.3 AC97 Controller Operation ................................................................................................................... 37-2
37.3.1 Block Diagram .............................................................................................................................. 37-2
37.3.2 Internal Data Path ......................................................................................................................... 37-3
37.3.3 Operation Flow Chart ................................................................................................................... 37-4
37.3.4 AC-link Digital Interface Protocol .................................................................................................. 37-5
37.3.5 AC-link Input Frame (SDATA_IN) ................................................................................................. 37-7
37.3.6 AC97 Power-Down ....................................................................................................................... 37-9
37.4 I/O Description ................................................................................................................................... 37-12
37.5 Register Description ........................................................................................................................... 37-13
37.5.1 Register Map Summary .............................................................................................................. 37-13
38 PCM AUDIO INTERFACE ......................................................................... 38-1
38.1 Overview .............................................................................................................................................. 38-1
38.2 Features ............................................................................................................................................... 38-1
38.3 PCM Audio Interface ............................................................................................................................ 38-2
38.4 PCM Timing ......................................................................................................................................... 38-3
38.5 I/O Description ..................................................................................................................................... 38-5
38.6 Register Description ............................................................................................................................. 38-6
38.6.1 Register Map Summary ................................................................................................................ 38-6
39 SPDIF TRANSMITTER .............................................................................. 39-1
39.1 Overview .............................................................................................................................................. 39-1
39.2 Features ............................................................................................................................................... 39-1
39.3 Block Diagram ...................................................................................................................................... 39-2
39.4 Functional Description ......................................................................................................................... 39-3
39.4.1 Data Format of SPDIF .................................................................................................................. 39-3
39.4.2 Channel Coding ............................................................................................................................ 39-6
39.4.3 Preamble ...................................................................................................................................... 39-6
39.4.4 Non-Linear PCM-Encoded Source (IEC 61937) .......................................................................... 39-7
39.4.5 SPDIF Operation .......................................................................................................................... 39-9
39.4.6 Shadowed Register .................................................................................................................... 39-10
39.5 I/O Description ................................................................................................................................... 39-11
39.6 Register Description ........................................................................................................................... 39-12
39.6.1 Register Map Summary .............................................................................................................. 39-12
40 CHIP TO CHIP (C2C) ................................................................................. 40-1
40.1 Overview .............................................................................................................................................. 40-1
40.2 Clock .................................................................................................................................................... 40-3
40.3 Address Mapping ................................................................................................................................. 40-4
40.3.1 Address Mapping Overview .......................................................................................................... 40-4
40.3.2 AP EMIF Address Mapping .......................................................................................................... 40-5
40.3.3 SSCM Address Mapping .............................................................................................................. 40-7
40.4 General Purpose Signals Mapping ...................................................................................................... 40-8
40.4.1 Overview ....................................................................................................................................... 40-8
40.4.2 GENI (General Purpose INPUT) Signals ..................................................................................... 40-8
40.4.3 GENO (General Purpose Output) Signals .................................................................................... 40-8
40.5 Sleep/Wake-up Scheme ...................................................................................................................... 40-9
40.5.1 AP Wake-up Procedure and Timing ............................................................................................. 40-9
40.5.2 CP Sleep Procedure ................................................................................................................... 40-12
40.6 Reset Scheme.................................................................................................................................... 40-14
40.6.1 Reset Cases ............................................................................................................................... 40-14
40.7 Boot-up Scheme ................................................................................................................................ 40-15
40.7.1 Reset & Start-up Sequence ........................................................................................................ 40-16
40.7.2 Keeping CP in Reset State before AP Ready for C2C ............................................................... 40-16
40.8 OPP Change Scheme ........................................................................................................................ 40-17
40.8.1 Increasing ................................................................................................................................... 40-17
40.8.2 Decreasing .................................................................................................................................. 40-18
40.8.3 I/O Description ............................................................................................................................ 40-19
40.9 Register Description ........................................................................................................................... 40-20
40.9.1 Register Map Summary .............................................................................................................. 40-20
41 HIGH-SPEED SYNCHRONOUS SERIAL INTERFACE (HSI) ................... 41-1
41.1 Overview .............................................................................................................................................. 41-1
41.2 Features ............................................................................................................................................... 41-1
41.3 Functional Description ......................................................................................................................... 41-2
41.3.1 Block Diagram .............................................................................................................................. 41-2
41.3.2 Interface Port Description ............................................................................................................. 41-4
41.3.3 Programming Basic Sequence Guide .......................................................................................... 41-5
41.4 Register Description ........................................................................................................................... 41-11
41.4.1 Register Map Summary .............................................................................................................. 41-11
42 DISPLAY CONTROLLER .......................................................................... 42-1
42.1 Overview .............................................................................................................................................. 42-1
42.2 Features of Display Controller ............................................................................................................. 42-2
42.3 Functional Description ......................................................................................................................... 42-4
42.3.1 Brief Description of the Sub-Block ................................................................................................ 42-4
42.3.2 Data Flow ...................................................................................................................................... 42-5
42.3.3 Overview of the Color Data .......................................................................................................... 42-8
42.3.4 Color Space Conversion ............................................................................................................. 42-23
42.3.5 Palette Usage ............................................................................................................................. 42-25
42.3.6 Window Blending ........................................................................................................................ 42-28
42.3.7 Image Enhancement .................................................................................................................. 42-37
42.3.8 VTIME Controller Operation ....................................................................................................... 42-44
42.3.9 Setting of Commands ................................................................................................................. 42-47
42.3.10 Virtual Display ........................................................................................................................... 42-50
42.3.11 RGB Interface Specification ..................................................................................................... 42-51
42.3.12 LCD Indirect i80 System Interface ............................................................................................ 42-60
42.4 I/O Description ................................................................................................................................... 42-64
42.5 Register Description ........................................................................................................................... 42-65
42.5.1 Register Map Summary .............................................................................................................. 42-66
42.5.2 Palette Memory ........................................................................................................................... 42-72
42.5.3 Control Register .......................................................................................................................... 42-73
42.5.4 Gamma Lookup Table .............................................................................................................. 42-145
42.5.5 Shadow Windows Control ........................................................................................................ 42-146
42.5.6 Palette Ram .............................................................................................................................. 42-147
43 CAMERA INTERFACE AND SCALER ...................................................... 43-1
43.1 Overview .............................................................................................................................................. 43-1
43.2 Features of CAMIF ............................................................................................................................... 43-3
43.3 External Interface ................................................................................................................................. 43-5
43.4 Timing Diagram and Data Alignment of Camera ................................................................................. 43-6
43.4.1 Timing Diagram of ITU Camera .................................................................................................... 43-6
43.4.2 MIPI CSI Data Alignment from MIPI Camera ............................................................................. 43-10
43.5 External Connection Guide ................................................................................................................ 43-11
43.6 Camera Interface Operation .............................................................................................................. 43-12
43.6.1 Input/Output DMA Ports ............................................................................................................. 43-12
43.6.2 Clock Domain ............................................................................................................................. 43-13
43.6.3 Frame Memory Hierarchy ........................................................................................................... 43-14
43.6.4 Memory Storing Method ............................................................................................................. 43-15
43.6.5 Timing Diagram for Register Setting .......................................................................................... 43-16
43.6.6 Timing Diagram for last IRQ ....................................................................................................... 43-18
43.6.7 Timing Diagram for IRQ (Memory Data Scaling Mode).............................................................. 43-20
43.6.8 Input DMA Feature ..................................................................................................................... 43-21
43.6.9 Camera Interlace Input Support ................................................................................................. 43-22
43.7 Input/Output Description .................................................................................................................... 43-23
43.8 Register Description ........................................................................................................................... 43-24
43.8.1 Register Map Summary .............................................................................................................. 43-24
44 FIMC_LITE (CAMERA INTERFACE) ........................................................ 44-1
44.1 Overview of Camera Interface in FIMC_LITE ...................................................................................... 44-1
44.1.1 Block Diagram .............................................................................................................................. 44-1
44.2 Timing Diagram and Data Alignment of Camera ................................................................................. 44-2
44.2.1 Parallel INTERFACE .................................................................................................................... 44-2
44.2.2 MIPI CSI Slave Interface .............................................................................................................. 44-3
44.2.3 Local Output Interface Data Alignment ........................................................................................ 44-4
44.3 External Connection Guide .................................................................................................................. 44-5
44.4 Input / Output Path ............................................................................................................................... 44-6
44.5 I/O Description ..................................................................................................................................... 44-7
44.6 Register Description ............................................................................................................................. 44-8
44.6.1 Register Map ................................................................................................................................ 44-8
45 MIPI-DSI MASTER .................................................................................... 45-1
45.1 Overview .............................................................................................................................................. 45-1
45.2 Features ............................................................................................................................................... 45-1
45.2.1 Block Diagram .............................................................................................................................. 45-2
45.2.2 Interfaces and Protocol ................................................................................................................. 45-6
45.2.3 Configuration .............................................................................................................................. 45-16
45.2.4 Dual Display versus Single Display ............................................................................................ 45-17
45.2.5 PLL ............................................................................................................................................. 45-18
45.2.6 Buffer .......................................................................................................................................... 45-18
45.3 I/O Description ................................................................................................................................... 45-19
45.4 Register Description ........................................................................................................................... 45-20
45.4.1 Register Map Summary .............................................................................................................. 45-20
45.5 DPHY PLL Control ............................................................................................................................. 45-39
45.5.1 PMS Setting Sample for MIPI PLL ............................................................................................. 45-39
46 MIPI-CSI SLAVE (MIPI-CSI) ...................................................................... 46-1
46.1 Overview of MIPI CSIS ........................................................................................................................ 46-1
46.2 Features ............................................................................................................................................... 46-1
46.3 Block Diagram ...................................................................................................................................... 46-2
46.4 Interface and Protocol .......................................................................................................................... 46-3
46.5 Data Format ......................................................................................................................................... 46-4
46.5.1 Data Alignment ............................................................................................................................. 46-4
46.5.2 YUV422 8-bit Order ...................................................................................................................... 46-4
46.6 I/O Description ..................................................................................................................................... 46-5
46.7 Register Description ............................................................................................................................. 46-6
46.7.1 Register Map Summary ................................................................................................................ 46-6
47 2D GRAPHIC ACCELERATOR ................................................................. 47-1
47.1 Overview .............................................................................................................................................. 47-1
47.2 Features ............................................................................................................................................... 47-2
47.2.1 Host Interface ............................................................................................................................... 47-2
47.2.2 Primitives ...................................................................................................................................... 47-2
47.2.3 Per-pixel Operation ....................................................................................................................... 47-3
47.2.4 Data Format .................................................................................................................................. 47-3
47.3 Host Interface: DMA Mode ................................................................................................................... 47-4
47.4 Color Format Conversion ..................................................................................................................... 47-9
47.4.1 RGBA Format ............................................................................................................................... 47-9
47.5 Rendering Pipeline ............................................................................................................................. 47-11
47.5.1 Primitive Drawing ........................................................................................................................ 47-12
47.5.2 Rotation and Addressing Direction (Flip) .................................................................................... 47-15
47.5.3 Clipping ....................................................................................................................................... 47-17
47.5.4 Color Key .................................................................................................................................... 47-18
47.5.5 Raster Operation ........................................................................................................................ 47-19
47.5.6 Mask Operation .......................................................................................................................... 47-21
47.5.7 Alpha Blending............................................................................................................................ 47-22
47.5.8 Fast Solid Color Fill..................................................................................................................... 47-26
47.6 Register Description ........................................................................................................................... 47-27
47.6.1 Register Map Summary .............................................................................................................. 47-27
47.6.2 General Registers ....................................................................................................................... 47-31
47.6.3 Command Registers ................................................................................................................... 47-37
47.6.4 Parameter Setting Registers ...................................................................................................... 47-43
47.6.5 Source ........................................................................................................................................ 47-45
47.6.6 Destination .................................................................................................................................. 47-50
47.6.7 Pattern ........................................................................................................................................ 47-54
47.6.8 Mask ........................................................................................................................................... 47-56
47.6.9 Clipping Window ......................................................................................................................... 47-60
47.6.10 ROP & Alpha Setting ................................................................................................................ 47-62
47.6.11 Color ......................................................................................................................................... 47-63
47.6.12 Color Key .................................................................................................................................. 47-65
47.6.13 Gamma Table ........................................................................................................................... 47-68
48 3D GRAPHIC ACCELERATOR (G3D) ...................................................... 48-1
48.1 Overview of G3D .................................................................................................................................. 48-1
48.2 Features of G3D................................................................................................................................... 48-2
48.3 Architecture Brief of G3D ..................................................................................................................... 48-3
48.4 G3D Structure ...................................................................................................................................... 48-4
48.5 GPU Hardware Architecture ................................................................................................................ 48-5
48.5.1 Top-level System .......................................................................................................................... 48-5
48.5.2 Functional Block Diagram of GPU Hardware Architecture ........................................................... 48-6
48.5.3 PMU Hardware Architecture ......................................................................................................... 48-8
48.5.4 Level 2 Cache Controller Hardware Architecture ......................................................................... 48-9
49 IMAGE ROTATOR ..................................................................................... 49-1
49.1 Overview of Image Rotator .................................................................................................................. 49-1
49.2 Features of Image Rotator ................................................................................................................... 49-1
49.3 Block Diagram ...................................................................................................................................... 49-2
49.4 Supported Image Rotation Functions .................................................................................................. 49-3
49.5 Image Rotation with Windows Offset ................................................................................................... 49-4
49.6 Programming Guide ............................................................................................................................. 49-5
49.6.1 Resister Setting ............................................................................................................................ 49-5
49.6.2 Restrictions on the Image Size ..................................................................................................... 49-5
49.7 Register Description ............................................................................................................................. 49-6
49.7.1 Register Map Summary ................................................................................................................ 49-6
50 JPEG CODEC ............................................................................................ 50-1
50.1 Overview .............................................................................................................................................. 50-1
50.2 Features ............................................................................................................................................... 50-2
50.3 Functional Description ......................................................................................................................... 50-4
50.3.1 Encoder Flow ................................................................................................................................ 50-4
50.3.2 Decoder Flow ................................................................................................................................ 50-6
50.3.3 Color Component Data Ordering .................................................................................................. 50-7
50.4 Programmer's Model ............................................................................................................................ 50-8
50.4.1 Encoder Flow Chart ...................................................................................................................... 50-8
50.4.2 Decoder Flow Chart ...................................................................................................................... 50-9
50.5 Register Description ........................................................................................................................... 50-10
50.5.1 Register Map Summary .............................................................................................................. 50-10
50.5.2 Programming QUAN_TBL_ENT and HUFF_TBL_ENT ............................................................. 50-26
50.6 Example Codes .................................................................................................................................. 50-28
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