TL/F/5306
MM54HC109A/MM74HC109A Dual J-K Flip-Flops with Preset and Clear
January 1988
MM54HC109A/MM74HC109A
Dual J-K
Flip-Flops with Preset and Clear
General Description
These J-K FLIP-FLOPS utilize advanced silicon-gate CMOS
technology to achieve the low power consumption and high
noise immunity of standard CMOS integrated circuits, along
with the ability to drive 10 LS-TTL loads.
Each flip flop has independent J, K
PRESET, CLEAR and
CLOCK inputs and Q and Q
outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
Y
Typical propagation delay: 20 ns
Y
Wide operating voltage range: 2–6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 40 mA maximum (74HC Series)
Y
Output drive capability: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5306–1
Top View
Order Number MM54HC109A or MM74HC109A
Function Table
Inputs Outputs
PR CLR CLK J K QQ
LH XXXHL
HL XXXLH
LL XXXH*H*
HH
u
LL L H
HH
u
H L TOGGLE
HH
u
L H Q0 Q0
HH
u
HH H L
HH LXXQ0Q
0
*This is an unstable condition, and is not guaranteed.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.