SATA 3.0协议详解：AHCI 1.3标准与未来PCIE趋势

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SATA 3.0 协议是Serial Advanced Technology Attachment (SATA)标准的最新版本，它是硬盘接口技术的重要组成部分，专为现代计算机系统设计，尤其是对于那些依赖于存储设备性能的用户和开发者而言。SATA 3.0在2008年6月26日被正式批准，其主要目标是提供更快的数据传输速度和更高效的硬盘控制。 AHCI (Advanced Host Controller Interface) 1.3 是SATA 3.0的一个关键部分，它定义了主机控制器与硬盘驱动器之间的高级通信规范。AHCI通过消除IDE协议中的瓶颈，如中断请求线和DMA同步问题，显著提升了数据传输速率。在SATA 3.0下，AHCI支持的最大理论数据传输速度可达6.0 Gbps（即600 MBps），相比早期版本有了显著提升。 AHCI 1.3规范包括了一系列改进，如减少了寻道时间、优化了错误检测和恢复机制、以及对多个磁盘的并行操作的支持。这些改进使得存储系统能够更好地处理大量并发读写请求，提高了系统的整体性能和响应速度。在下载AHCI 1.3规格时，可以从Intel Developer网站获取，这意味着它是由Intel等公司制定和维护的，用户在使用时需要注意的是，该规范是“按现状提供”，不附带任何形式的保修或保证，包括对适配特定用途的保证。此外，用户在实施或使用其中的信息时，必须自行承担可能侵犯知识产权的风险，因为作者不对因使用此规范而产生的侵权行为负责。 SATA 3.0协议及其AHCI 1.3版本是现代计算机架构中不可或缺的一部分，对于追求高数据传输效率和存储性能的用户来说，理解并掌握这些技术细节至关重要。随着PCIe逐渐成为主流，了解SATA 3.0仍是扩展和优化存储解决方案时的重要参考，但未来的发展趋势也表明了持续学习和适应新技术的必要性。

Serial ATA AHCI 1.3 Specification

02 RW 0

Bus Master Enable (BME): Controls the HBA’s ability to act as a master for data

transfers. When set to ‘1’, bus master activity is allowed. When cleared to ‘0’, the HBA

stops and any active DMA engines return to an idle condition. It is the equivalent of

clearing the memory space start bits (PxCMD.ST) in each port.

01 RW 0

Memory Space Enable (MSE): Controls access to the HBA’s register memory space.

RW/

Impl

Spec

I/O Space Enable (IOSE): Controls access to the HBA’s target I/O space. If the HBA

also supports bus master IDE, this bit must be read/write. This bit should be read-only

if bus master IDE is not supported by the HBA.

2.1.3 Offset 06h: STS - Device Status

Bit Type Reset Description

15 RWC 0

Detected Parity Error (DPE): Set to ‘1’ by hardware when the HBA detects a parity

error on its interface.

14 RWC 0

Signaled System Error (SSE): Set to ‘1’ by hardware when the HBA host generates

SERR#.

13 RWC 0

Received Master-Abort (RMA): Set to ‘1’ by hardware when the HBA receives a

master abort to a cycle it generated.

12 RWC 0

Received Target Abort (RTA): Set to ‘1’ by hardware when the HBA receives a target

abort to a cycle it generated.

11 RWC 0

Signaled Target-Abort (STA): Set to ‘1’ by hardware when the HBA terminates with a

target abort.

10:09 RO

Impl.

Spec.

DEVSEL# Timing (DEVT): Controls the device select time for the HBA’s PCI interface.

Refer to the PCI specification for further details.

08 RWC 0

Master Data Pariy Error Detected (DPD): Set to ‘1’ by hardware when the HBA, as a

master, either detects a parity error or sees the parity error line asserted, and the parity

error response bit (bit 6 of the command register) is set to ‘1’.

07 RO

Impl.

Spec.

Fast Back-to-Back Capable (FBC): Indicates whether the HBA can accept fast back-

to-back cycles.

06 RO 0 Reserved

05 RO

Impl.

Spec.

66 MHz Capable (C66): Indicates whether the HBA can operate at 66 MHz.

04 RO 1

Capabilities List (CL): Indicates the presence of a capabilities list. The HBA must

support the PCI power management capability as a minimum.

03 RO 0

Interrupt Status (IS): Indicates the interrupt status of the device (1 = asserted).

02:00 RO 0 Reserved

2.1.4 Offset 08h: RID - Revision ID

Bits Type Reset Description

07:00 RO 00h

Revision ID (RID): Indicates stepping of the HBA hardware.

2.1.5 Offset 09h: CC - Class Code

Bits Type Reset Description

23:16 RO 01h

Base Class Code (BCC): Indicates that this is a mass storage device.

15:08 RO

Impl

Spec

Sub Class Code (SCC): When set to 06h, indicates that this is a Serial ATA device.

07:00 RO

Impl

Spec

Programming Interface (PI): When set to 01h and the Sub Class Code is set to 06h,

indicates that this is an AHCI HBA that has a major revision of 1 (as specified in the

AHCI Version register).

Informative Note: For HBAs that support RAID, the Sub Class Code reset value should be 04h and the

Programming Interface reset value should be 00h.

2.1.6 Offset 0Ch: CLS – Cache Line Size

Bits Type Reset Description

07:00 RW 00h

Cache Line Size (CLS): Indicates the cache line size for use with the memory write

and invalidate command, and as an indication on when to use the memory read

multiple, memory read line, or memory read commands.

Serial ATA AHCI 1.3 Specification

2.1.7 Offset 0Dh: MLT – Master Latency Timer

Bits Type Reset Description

07:00 RW 00h

Master Latency Timer (MLT): Indicates the number of clocks the HBA is allowed to act

as a master on PCI.

2.1.8 Offset 0Eh: HTYPE – Header Type

Bits Type Reset Description

07 RO

Impl

Spec

Multi-Function Device (MFD): Indicates whether the HBA is part of a multi-function

device.

06:00 RO 00h

Header Layout (HL): Indicates that the HBA uses a target device layout.

2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional)

The following register is optional, but if implemented, must look as follows.

Bits Type Reset Description

07 RO 1

BIST Capable (BC): Indicates whether the HBA has a BIST function. This does not

indicate SATA BIST capability – this is only for an HBA related BIST function.

06 RW 0

Stat BIST (SB): Software sets this bit to ‘1’ to invoke BIST. The HBA clears this bit to

‘0’ when BIST is complete.

05:04 RO 00 Reserved

03:00 RO 0h

Completion Code (CC): Indicates the completion code status of BIST. A non-zero

value indicates a failure.

2.1.10 Offset 10h – 20h: BARS – Other Base Addresses (Optional)

These registers allocate memory or I/O spaces for other BARs. An example application of these BARs is

to implement the native IDE and bus master IDE ranges for an HBA that wishes to support legacy

software.

2.1.11 Offset 24h: ABAR – AHCI Base Address

This register allocates space for the HBA memory registers defined in section

3. The ABAR must be

allocated to contain enough space for the global AHCI registers, the port specific registers for each port,

and any vendor specific space (if needed). It is permissible to have vendor specific space after the port

specific registers for the last HBA port.

Bit Type Reset Description

31:13 RW 0

Base Address (BA): Base address of register memory space. This represents a

memory space for support of 32 ports. For HBAs that support fewer than 32-ports,

more bits are allowed to be RW, and therefore less memory space is consumed. For

HBAs that have vendor specific space at the end of the port specific memory space,

more bits are allowed to be RO such that more memory space is consumed.

12:04 RO 0 Reserved

03 RO 0

Prefetchable (PF): Indicates that this range is not pre-fetchable

02:01 RO 00

Type (TP): Indicates that this range can be mapped anywhere in 32-bit address space

00 RO 0

Resource Type Indicator (RTE): Indicates a request for register memory space.

2.1.12 Offset 2Ch: SS - Sub System Identifiers

Bits Type Reset Description

31:16 RO

Impl

Spec

Subsystem ID (SSID): Indicates the sub-system identifier.

15:00 RO

Impl

Spec

Subsystem Vendor ID (SSVID): Indicates the sub-system vendor identifier

2.1.13 Offset 30h: EROM – Expansion ROM (Optional)

Bit Type Reset Description

31:00 RW

Impl

Spec

ROM Base Address (RBA): Indicates the base address of the HBA expansion ROM.

Serial ATA AHCI 1.3 Specification

.1.14 Offset 34h: CAP – Capabilities Pointer

Bit Type Reset Description

7:0 RO PMCAP

Capability Pointer (CP): Indicates the first capability pointer offset. It points to

the PCI Power management capability offset.

2.1.15 Offset 3Ch: INTR - Interrupt Information

Bits Type Reset Description

15:08 RO

Impl

Spec

Interrupt Pin (IPIN): This indicates the interrupt pin the HBA uses.

07:00 RW 00h

Interrupt Line (ILINE): Software written value to indicate which interrupt line (vector)

the interrupt is connected to. No hardware action is taken on this register.

Informative Note: If the HBA is a single function PCI device, then INTR.IPIN should be set to 01h to

indicate the INTA# pin.

2.1.16 Offset 3Eh: MGNT – Minimum Grant (Optional)

Bits Type Reset Description

07:00 RO

Impl

Spec

Grant (GNT): Indicates the minimum grant time (in ¼ microseconds) that the device

wishes grant asserted.

2.1.17 Offset 3Fh: MLAT – Maximum Latency (Optional)

Bits Type Reset Description

07:00 RO

Impl

Spec

Latency (LAT): Indicates the maximum latency (in ¼ microseconds) that the device

can withstand.

2.2 PCI Power Management Capabilities

Start (hex) End (hex) Symbol Name

PMCAP PMCAP+1 PID PCI Power Management Capability ID

PMCAP+2 PMCAP+3 PC PCI Power Management Capabilities

PMCAP+4 PMCAP+5 PMCS PCI Power Management Control and Status

2.2.1 Offset PMCAP: PID - PCI Power Management Capability ID

Bit Type Reset Description

15:08 RO

Impl

Spec

Next Capability (NEXT): Indicates the location of the next capability item in the

list. This can be other capability pointers (such as Message Signaled Interrupts,

PCI-X, or PCI-Express) or it can be the last item in the list.

07:00 RO 01h

Cap ID (CID): Indicates that this pointer is a PCI power management.

2.2.2 Offset PMCAP + 2h: PC – PCI Power Management Capabilities

Bit Type Reset Description

15:11 RO

Impl

Spec

PME_Support (PSUP): Indicates the states that can generate PME#. The encoding of

this field is as follows:

Bit State

15 When set to ‘1’, PME# can be generated from D3

COLD

. When cleared

to ‘0’, PME# cannot be generated from D3

COLD

. This bit may be a ‘1’

or ‘0’ for AHCI HBAs.

14 When set to ‘1’, PME# can be generated from D3

HOT

. When cleared

to ‘0’, PME# cannot be generated from D3

HOT

. This bit must be ‘1’ for

AHCI HBAs.

13 This bit must be ‘0’ for AHCI HBAs. D2 is not a supported HBA state.

The behavior is undefined if the HBA is placed in this state.

12 This bit must be ‘0’ for AHCI HBAs. D1 is not a supported HBA state.

The behavior is undefined if the HBA is placed in this state.

11 This bit must be ‘0’ for AHCI HBAs. PME# from D0 is not supported

– interrupts are used in D0.

Serial ATA AHCI 1.3 Specification

10 RO 0

D2_Support (D2S): The D2 state is not supported for AHCI HBAs.

09 RO 0

D1_Support (D1S): The D1 state is not supported for AHCI HBAs.

08:06 RO

Impl

Spec

Aux_Current (AUXC): Reports the maximum Suspend well current required when in

the D3

COLD

state. Refer to the PCI specification for definition of values.

05 RO

Impl

Spec

Device Specific Initialization (DSI): Indicates whether device-specific initialization is

required.

04 RO 0 Reserved

03 RO 0

PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#.

02:00 RO

Impl

Spec

Version (VS): Indicates support for Revision 1.1 or higher revisions of the PCI Power

Management Specification.

2.2.3 Offset PMCAP + 4h: PMCS – PCI Power Management Control And Status

Bit Type Reset Description

15 RWC

Impl

Spec

PME Status (PMES): Set to ‘1’ by hardware when the HBA generates PME#.

If the HBA supports waking from D3

COLD

, this bit is indeterminate at system boot. If the

HBA does not support waking from D3

COLD

, this bit is ‘0’ at system boot.

14:09 RO 0 Reserved – AHCI HBA does not implement the data register.

08 RW

Impl

Spec

PME Enable (PMEE): When set to ‘1’, the HBA asserts the PME# signal when PMES

is set to ‘1’.

If the HBA supports waking from D3

COLD

, this bit is indeterminate at system boot. If the

HBA does not support waking from D3

COLD

, this bit is ‘0’ at system boot.

07:02 RO 0 Reserved

01:00 R/W 00

Power State (PS): This field is used both to determine the current power state of the

HBA and to set a new power state. The values are:

00 – D0 state

11 – D3

HOT

state

The D1 and D2 states are not supported for AHCI HBAs. When in the D3

HOT

state, the

HBA’s configuration space is available, but the register memory spaces are not.

Additionally, interrupts are blocked.

2.3 Message Signaled Interrupt Capability (Optional)

Start (hex) End (hex) Symbol Name

MSICAP MSICAP+1 MID Message Signaled Interrupt Capability ID

MSICAP+2 MSICAP+3 MC Message Signaled Interrupt Message Control

MSICAP+4 MSICAP+7 MA Message Signaled Interrupt Message Address

MSICAP+8 (MC.C64=0)

MSICAP+C (MC.C64=1)

MSICAP+9

MSICAP.D

MD Message Signaled Interrupt Message Data

MSICAP+8 (MC.C64=1) MSICAP+B MUA Message Signaled Interrupt Upper Address (Optional)

2.3.1 Offset MSICAP: MID – Message Signaled Interrupt Identifiers

Bits Type Reset Description

15:08 RO

Impl

Spec

Next Pointer (NEXT): Indicates the next item in the list. This can be other capability

pointers (such as PCI-X or PCI-Express) or it can be the last item in the list.

07:00 RO 05h

Capability ID (CID): Capabilities ID indicates MSI.

2.3.2 Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control

Bits Type Reset Description

15:08 RO 0 Reserved

07 RO

Impl

Spec

64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit

messages.

06:04 RW 000

Multiple Message Enable (MME): Indicates the number of messages the HBA should

assert. See section 10.7.2.2. If the value programmed into this field exceeds the MMC

field in this register, the results are indeterminate.

03:01 RO

Impl

Spec

Multiple Message Capable (MMC): Indicates the number of messages the HBA

wishes to assert. See section

10.7.2.2.

00 RW 0

MSI Enable (MSIE): If set to ‘1’, MSI is enabled and the traditional interrupt pins are not

Serial ATA AHCI 1.3 Specification

used to generate interrupts. If cleared to ‘0’, MSI operation is disabled and the

traditional interrupt pins are used.

2.3.3 Offset MSICAP + 4h: MA – Message Signaled Interrupt Message Address

Bits Type Reset Description

31:02 RW 0

Address (ADDR): Lower 32 bits of the system specified message address, always DW

aligned.

01:00 RO 00 Reserved

2.3.4 Offset MSICAP + (8h or Ch): MD – Message Signaled Interrupt Message Data

Bits Type Reset Description

15:00 RW 0

Data (Data): This 16-bit field is programmed by system software if MSI is enabled. Its

content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI

memory write transaction.

2.3.5 Offset MSICAP + 8h: MUA – Message Signaled Interrupt Upper Address (Optional)

Bits Type Reset Description

31:00 RW 0

Upper Address (UADDR):

Upper 32 bits of the system specified message

address. This register is optional and only implemented if MC.C64=1.

2.4 Serial ATA Capability (Optional)

This set of registers when supported is used for the Index-Data Pair mechanism described in section

10.14.

Start (hex) End (hex) Symbol Name

SATACAP SATACAP+3 SATACR0 Serial ATA Capability Register 0

SATACAP+4 SATACAP+7 SATACR1 Serial ATA Capability Register 1

2.4.1 Offset SATACAP: SATACR0 – Serial ATA Capability Register 0

Bit Type Reset Description

31:24 RO 0h Reserved

23:20 RO 1h

Major Revision (MAJREV): Major revision number of the SATA Capability

Pointer implemented.

19:16 RO 0h

Minor Revision (MINREV): Minor revision number of the SATA Capability Pointer

implemented.

15:08 RO

Impl

Spec

Next Capability (NEXT): Indicates the location of the next capability item in the

list. This can be other capability pointers (such as Message Signaled Interrupts,

PCI-X, or PCI-Express) or it can be the last item in the list.

07:00 RO 12h

Cap ID (CID): Indicates that this pointer is a SATA Capability.

2.4.2 Offset SATACAP + 4h: SATACR1 – Serial ATA Capability Register 1

Bit Type Reset Description

31:24 RO 0 Reserved

23:4 RO

Impl

Spec

BAR Offset (BAROFST): Indicates the offset into the BAR where the Index-Data Pair

are located in Dword granularity. Possible values include:

000h = 0h offset

001h = 4h offset

002h = 8h offset

003h = Ch offset

004h = 10h offset

…

3FFFh = FFFCh offset

Maximum if Index-Data Pair is implemented in IO Space from 0 – 64 KB

3FFFFh = FFFFCh offset

Maximum if Index-Data Pair is memory mapped in the 0 – (1MB – 4) range)

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