高速突发模式时钟数据恢复IC设计

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"Design of High-speed Burst Mode Clock and Data Recovery IC for Passive Optical Network" 这篇论文主要探讨了在光通信领域，特别是在吉比特无源光网络（GPON）中设计高速突发模式时钟和数据恢复（BMCDR）集成电路的关键技术和挑战。BMCDR电路对于在高速数据传输中保持信号同步和质量至关重要。首先，文章提出了一个自顶向下的设计流程，这是一种常见的集成电路设计方法，它从系统级开始，逐步细化到电路级。在面对BMCDR集成电路的复杂性时，这种方法有助于系统地处理设计问题。作者特别关注行为级建模，这是设计流程中的重要步骤，因为它能提供对电路行为的高级理解，且易于调整和优化。为了应对频率控制电压饱和问题，文中介绍了精确的Simulink行为模型的实现。Simulink是一种用于动态系统建模和仿真工具，通过这个模型，可以更准确地模拟和预测电路在不同条件下的行为。这使得设计师能够根据模型参数调整和优化电路块，确保整个系统的性能。在技术实现上，新的BMCDR设计采用了0.18微米的标准CMOS工艺。这种工艺因其高集成度和相对较低的功耗，在高速集成电路中广泛应用。据文中所述，该设计能够支持2.5Gbps的比特率，这是GPON中常见的数据传输速率，同时在模拟测试中，其恢复时间仅为一个比特周期，这意味着数据恢复速度快且效率高。最后，行为模型的正确性通过与详细电路模拟的对比得到了验证。这一验证过程是确保设计有效性和可靠性的关键步骤，确保在实际硬件实施前，设计方案已经在理论上达到了预期性能。这篇论文展示了在高速光通信系统中，如何设计并优化一个高效的BMCDR集成电路，它在GPON环境下能够有效地处理高比特率数据，实现快速的数据恢复，同时利用先进的CMOS工艺降低功耗和提高集成度。这些成果对于提升光网络的传输性能和稳定性具有重要意义。

Design of High-speed Burst Mode Clock and Data Recovery IC

for Passive Optical Network

Minhui Yan

, Xiaobin Hong

, Wei-Ping Huang

, Jin Hong

Department of Electrical and Computer Engineering, McMaster University,

Hamilton, ON L8S4K1, Canada;

Oplink Communications Inc., 46335 Landing Parkway, Fremont, CA 94538, USA

ABSTRACT

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks

(GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level

modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise

implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore

developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the

behavioural model. The newly designed BMCDR utilizes the 0.18µm standard CMOS technology and is shown to be

capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The

developed behaviour model is verified by comparing with the detailed circuit simulation.

Keywords: burst mode, clock and data recovery, gated oscillator, passive optical network

1. INTRODUCTION

Passive optical networks (PON), such as the Ethernet PON (EPON) and the Giga PON (GPON), are currently most

sought-after candidates for the Fiber-to-the-Home (FTTH) applications, due to primarily their good balance between the

economy and the performance of the networks. It is economical for the service providers since it saves fibers and optical

line terminals (OLTs), therefore reduces the capital expenditure (CAPEX) for PON deployment. However, it brings new

challenges to the design of optical transceivers, which is particularly acute in the case of the receivers for the OLTs. For

example, the optical packets received by the OLTs are in burst mode operation, which means their amplitudes and phases

vary from packet to packet. Therefore the clock and data recovery (CDR) circuit must be capable of instantaneous

synchronization with the incoming data. This type of CDR is normally referred to as the burst mode CDR or BMCDR in

this paper.

In general, BMCDR can be divided into two categories, digital and mixed-signal. Compared with various schemes of the

digital forms

1,2

, the implementation of the mixed-signal BMCDR usually employs gated oscillator (GO) from its first

invention

. It was then further developed with different topology variations

, increase in speed

, addition of

supplementary circuit

, and etc. Other kinds of mixed-signal architectures have also been reported, for example, using

muxed oscillators

or novel phase detectors

. However, to the authors’ best knowledge, the highest operation speed of the

design with frequency control mechanism achieved so far is at 1.25Gbps

, although there were also designs working at

10Gbps but not with the frequency control mechanism

. The design of our work is targeted for 2.5Gbps BMCDR with

frequency control, based on 0.18µm standard CMOS technology, which is one of our main contributions in this work.

Among all the previous publications, none of them gave a design flow to provide the step by step procedure of designing

a working BMCDR. However, complex design concepts may need to be modeled and verified in an abstract behavioural

level in the initial design stage, which can then ease the optimization of the key parameters

. Nevertheless, detailed

circuit simulation, for example, by the use of Spectre

, is still required for lower level design and circuit performance

simulation at later design steps. Behavioural level simulation can save the simulation time significantly. For this purpose,

we employ the Simulink/Matlab

model, which takes only minutes, in comparison with the more detailed circuit models

such as the Spectre simulation which normally cost hours for the same circuit. Simulink is a good candidate for high

level simulation of complex systems, such as Phase-Locked Loop (PLL) or frequency synthesizer

10,13

. In this paper, we

Photonic Applications in Devices and Communication Systems, edited by Peter Mascher, Andrew P. Knights,

John C. Cartledge, David V. Plant, Proc. of SPIE Vol. 5970, 59702W, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.628728

Proc. of SPIE Vol. 5970 59702W-1

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高速突发模式时钟数据恢复IC设计

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clock data recovery cdr 时钟数据恢复专利