Design of High-speed Burst Mode Clock and Data Recovery IC
for Passive Optical Network
Minhui Yan
a
, Xiaobin Hong
a
, Wei-Ping Huang
a
, Jin Hong
b
a
Department of Electrical and Computer Engineering, McMaster University,
Hamilton, ON L8S4K1, Canada;
b
Oplink Communications Inc., 46335 Landing Parkway, Fremont, CA 94538, USA
ABSTRACT
Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks
(GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level
modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise
implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore
developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the
behavioural model. The newly designed BMCDR utilizes the 0.18µm standard CMOS technology and is shown to be
capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The
developed behaviour model is verified by comparing with the detailed circuit simulation.
Keywords: burst mode, clock and data recovery, gated oscillator, passive optical network
1. INTRODUCTION
Passive optical networks (PON), such as the Ethernet PON (EPON) and the Giga PON (GPON), are currently most
sought-after candidates for the Fiber-to-the-Home (FTTH) applications, due to primarily their good balance between the
economy and the performance of the networks. It is economical for the service providers since it saves fibers and optical
line terminals (OLTs), therefore reduces the capital expenditure (CAPEX) for PON deployment. However, it brings new
challenges to the design of optical transceivers, which is particularly acute in the case of the receivers for the OLTs. For
example, the optical packets received by the OLTs are in burst mode operation, which means their amplitudes and phases
vary from packet to packet. Therefore the clock and data recovery (CDR) circuit must be capable of instantaneous
synchronization with the incoming data. This type of CDR is normally referred to as the burst mode CDR or BMCDR in
this paper.
In general, BMCDR can be divided into two categories, digital and mixed-signal. Compared with various schemes of the
digital forms
1,2
, the implementation of the mixed-signal BMCDR usually employs gated oscillator (GO) from its first
invention
3
. It was then further developed with different topology variations
4
, increase in speed
5
, addition of
supplementary circuit
6
, and etc. Other kinds of mixed-signal architectures have also been reported, for example, using
muxed oscillators
7
or novel phase detectors
8
. However, to the authors’ best knowledge, the highest operation speed of the
design with frequency control mechanism achieved so far is at 1.25Gbps
5
, although there were also designs working at
10Gbps but not with the frequency control mechanism
9
. The design of our work is targeted for 2.5Gbps BMCDR with
frequency control, based on 0.18µm standard CMOS technology, which is one of our main contributions in this work.
Among all the previous publications, none of them gave a design flow to provide the step by step procedure of designing
a working BMCDR. However, complex design concepts may need to be modeled and verified in an abstract behavioural
level in the initial design stage, which can then ease the optimization of the key parameters
10
. Nevertheless, detailed
circuit simulation, for example, by the use of Spectre
11
, is still required for lower level design and circuit performance
simulation at later design steps. Behavioural level simulation can save the simulation time significantly. For this purpose,
we employ the Simulink/Matlab
12
model, which takes only minutes, in comparison with the more detailed circuit models
such as the Spectre simulation which normally cost hours for the same circuit. Simulink is a good candidate for high
level simulation of complex systems, such as Phase-Locked Loop (PLL) or frequency synthesizer
10,13
. In this paper, we
Photonic Applications in Devices and Communication Systems, edited by Peter Mascher, Andrew P. Knights,
John C. Cartledge, David V. Plant, Proc. of SPIE Vol. 5970, 59702W, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.628728
Proc. of SPIE Vol. 5970 59702W-1