"计算机组成与设计：硬件/软件接口的赞歌——选择教材不再是妥协"

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《计算机组成与设计：硬件/软件接口（RISC-V版）》是一本在各个方面无可挑剔的计算机组成教材。它涵盖了计算机组成和设计的重要内容，并且以出色的教学理念和严谨的层次，深入浅出地向读者阐述了相关知识。这本书不仅仅是一本计算机组成教材，更是其他计算机科学教材应当效仿的典范。该书作者是David A. Patterson和John L. Hennessy，两位享誉全球的计算机科学家，他们的经验和思想为这本教材带来了非凡的价值。书中以RISC-V架构为基础，全面地介绍了计算机组成与设计的各个方面，包括数字逻辑、指令集体系结构、处理器设计、存储器层次结构、输入输出和并行处理等内容。同时，书中还特别关注了硬件和软件之间的接口，这是当今计算机体系结构中不可忽视的重要部分。教材从浅显易懂的角度出发，通过丰富的图表和实例，深入浅出地向读者介绍了计算机组成的复杂性。与传统教材相比，该书采用了全新的教学方法，注重在读者的学习过程中培养思考和解决问题的能力。这种积极的教学方法引导读者从理论到实践，从而深入理解计算机组成的原理和设计方法。编写教材的过程中，作者非常注重内容的完整性和准确性。书中所涵盖的知识点广泛而深入，能够满足不同读者的需求。无论是计算机科学专业的学生，还是对计算机组成有兴趣的业余爱好者，都能从中受益匪浅。此外，书中所提供的习题和实践项目，可以帮助读者更好地掌握所学知识，并加深对计算机组成的理解。与内容的优秀性相匹配的是该教材的教学素材和资源丰富。在教材的官方网站上，读者可以找到相关课件、习题解答、实验指导、代码例程等丰富的教学资源。这些资源不仅可以作为教学工具，也方便了读者在自学过程中的参考和实践。同时，作者还根据新技术的发展和行业需求，不断更新和完善这些教学资源，使之始终保持与教材内容的同步性和实用性。此外，该书还考虑到了教材的价格问题。相比其他计算机组成教材，该教材的价格相对较低，且印刷质量和装订都非常出色。这使得教材更容易被广大学生和教师所接触和使用。总之，《计算机组成与设计：硬件/软件接口（RISC-V版）》是一本让人满意的计算机组成教材。它凭借其全面而深入的内容、出色的教学方法和丰富的教学资源，成为计算机科学领域的经典之作。无论是作为课堂教学的辅助工具，还是作为自学的参考书，该教材都能够为读者提供丰富的知识和良好的学习体验。

Preface

e most beautiful thing we can experience is the mysterious. It is the

source of all true art and science.

Albert Einstein, What I Believe, 1930

About This Book

We believe that learning in computer science and engineering should reect

the current state of the eld, as well as introduce the principles that are shaping

computing. We also feel that readers in every specialty of computing need

to appreciate the organizational paradigms that determine the capabilities,

performance, energy, and, ultimately, the success of computer systems.

Modern computer technology requires professionals of every computing

specialty to understand both hardware and soware. e interaction between

hardware and soware at a variety of levels also oers a framework for understanding

the fundamentals of computing. Whether your primary interest is hardware or

soware, computer science or electrical engineering, the central ideas in computer

organization and design are the same. us, our emphasis in this book is to show

the relationship between hardware and soware and to focus on the concepts that

are the basis for current computers.

e recent switch from uniprocessor to multicore microprocessors conrmed

the soundness of this perspective, given since the rst edition. While programmers

could ignore the advice and rely on computer architects, compiler writers, and silicon

engineers to make their programs run faster or be more energy-ecient without

change, that era is over. For programs to run faster, they must become parallel.

While the goal of many researchers is to make it possible for programmers to be

unaware of the underlying parallel nature of the hardware they are programming,

it will take many years to realize this vision. Our view is that for at least the next

decade, most programmers are going to have to understand the hardware/soware

interface if they want programs to run eciently on parallel computers.

e audience for this book includes those with little experience in assembly

language or logic design who need to understand basic computer organization as

well as readers with backgrounds in assembly language and/or logic design who

want to learn how to design a computer or understand how a system works and

why it performs as it does.

xvi Preface

About the Other Book

Some readers may be familiar with Computer Architecture: A Quantitative

Approach, popularly known as Hennessy and Patterson. (is book in turn is

oen called Patterson and Hennessy.) Our motivation in writing the earlier book

was to describe the principles of computer architecture using solid engineering

fundamentals and quantitative cost/performance tradeos. We used an approach

that combined examples and measurements, based on commercial systems, to

create realistic design experiences. Our goal was to demonstrate that computer

architecture could be learned using quantitative methodologies instead of a

descriptive approach. It was intended for the serious computing professional who

wanted a detailed understanding of computers.

A majority of the readers for this book do not plan to become computer

architects. e performance and energy eciency of future soware systems will

be dramatically aected, however, by how well soware designers understand the

basic hardware techniques at work in a system. us, compiler writers, operating

system designers, database programmers, and most other soware engineers

need a rm grounding in the principles presented in this book. Similarly,

hardware designers must understand clearly the eects of their work on soware

applications.

us, we knew that this book had to be much more than a subset of the material

in Computer Architecture, and the material was extensively revised to match the

dierent audience. We were so happy with the result that the subsequent editions

of Computer Architecture were revised to remove most of the introductory

material; hence, there is much less overlap today than with the rst editions of

both books.

Why RISC-V for This Edition?

e choice of instruction set architecture is clearly critical to the pedagogy of a

computer architecture textbook. We didn’t want an instruction set that required

describing unnecessary baroque features for someone’s rst instruction set, no

matter how popular it is. Ideally, your initial instruction set should be an exemplar,

just like your rst love. Surprisingly, you remember both fondly.

Since there were so many choices at the time, for the rst edition of Computer

Architecture: A Quantitative Approach we invented our own RISC-style instruction

set. Given the growing popularity and the simple elegance of the MIPS instruction

set, we switched to it for the rst edition of this book and to later editions of the

other book. MIPS has served us and our readers well.

It’s been 20 years since we made that switch, and while billions of chips that use

MIPS continue to be shipped, they are typically in found embedded devices where

the instruction set is nearly invisible. us, for a while now it’s been hard to nd a

real computer on which readers can download and run MIPS programs.

e good news is that an open instruction set that adheres closely to the RISC

principles has recently debuted, and it is rapidly gaining a following. RISC-V, which

was developed originally at UC Berkeley, not only cleans up the quirks of the MIPS

Preface xvii

instruction set, but it oers a simple, elegant, modern take on what instruction sets

should look like in 2017.

Moreover, because it is not proprietary, there are open-source RISC-V simulators,

compilers, debuggers, and so on easily available and even open-source RISC-V

implementations available written in hardware description languages. In addition,

there will soon be low-cost hardware platforms on which to run RISC-V programs.

Readers will not only benet from studying these RISC-V designs, they will be able

to modify them and go through the implementation process in order to understand

the impact of their hypothetical changes on performance, die size, and energy.

is is an exciting opportunity for the computing industry as well as for

education, and thus at the time of this writing more than 40 companies have joined

the RISC-V foundation. is sponsor list includes virtually all the major players

except for ARM and Intel, including AMD, Google, Hewlett Packard Enterprise,

IBM, Microso, NVIDIA, Oracle, and Qualcomm.

It is for these reasons that we wrote a RISC-V edition of this book, and we are

switching Computer Architecture: A Quantitative Approach to RISC-V as well.

Given that RISC-V oers both 32-bit address instructions and 64-bit address

instructions with essentially the same instruction set, we could have switched

instruction sets but kept the address size at 32 bits. Our publisher polled the faculty

who used the book and found that 75% either preferred larger addresses or were

neutral, so we increased the address space to 64 bits, which may make more sense

today than 32 bits.

e only changes for the RISC-V edition from the MIPS edition are those

associated with the change in instruction sets, which primarily aects Chapter2,

Chapter3, the virtual memory section in Chapter5, and the short VMIPS example

in Chapter6. In Chapter4, we switched to RISC-V instructions, changed several

gures, and added a few “Elaboration” sections, but the changes were simpler than

we had feared. Chapter1 and the rest of the appendices are virtually unchanged.

e extensive online documentation and combined with the magnitude of RISC-V

make it dicult to come up with a replacement for the MIPS version of Appendix

A (“Assemblers, Linkers, and the SPIM Simulator” in the MIPS Fih Edition).

Instead, Chapters2, 3, and 5 include quick overviews of the hundreds of RISC-V

instructions outside of the core RISC-V instructions that we cover in detail in the

rest of the book.

Note that we are not (yet) saying that we are permanently switching to RISC-V. For

example, in addition to this new RISC-V edition, there are ARMv8 and MIPS versions

available for sale now. One possibility is that there will be a demand for all versions for

future editions of the book, or for just one. We’ll cross that bridge when we come to it.

For now, we look forward to your reaction to and feedback on this eort.

Changes for the Fifth Edition

We had six major goals for the h edition of Computer Organization and Design

demonstrate the importance of understanding hardware with a running example;

highlight main themes across the topics using margin icons that are introduced

xviii Preface

early; update examples to reect changeover from PC era to post-PC era; spread

the material on I/O throughout the book rather than isolating it into a single

chapter; update the technical content to reect changes in the industry since the

publication of the fourth edition in 2009; and put appendices and optional sections

online instead of including a CD to lower costs and to make this edition viable as

an electronic book.

Before discussing the goals in detail, let’s look at the table on the next page. It

shows the hardware and soware paths through the material. Chapters1, 4, 5, and

6 are found on both paths, no matter what the experience or the focus. Chapter1

discusses the importance of energy and how it motivates the switch from single

core to multicore microprocessors and introduces the eight great ideas in computer

architecture. Chapter2 is likely to be review material for the hardware-oriented,

but it is essential reading for the soware-oriented, especially for those readers

interested in learning more about compilers and object-oriented programming

languages. Chapter 3 is for readers interested in constructing a datapath or in

learning more about oating-point arithmetic. Some will skip parts of Chapter3,

either because they don’t need them, or because they oer a review. However, we

introduce the running example of matrix multiply in this chapter, showing how

subword parallels oers a fourfold improvement, so don’t skip Sections 3.6 to 3.8.

Chapter4 explains pipelined processors. Sections 4.1, 4.5, and 4.10 give overviews,

and Section 4.12 gives the next performance boost for matrix multiply for those

with a soware focus. ose with a hardware focus, however, will nd that this

chapter presents core material; they may also, depending on their background,

want to read Appendix A on logic design rst. e last chapter, on multicores,

multiprocessors, and clusters, is mostly new content and should be read by

everyone. It was signicantly reorganized in this edition to make the ow of

ideas more natural and to include much more depth on GPUs, warehouse-scale

computers, and the hardware–soware interface of network interface cards that

are key to clusters.

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