Microchip LAN8742A：高性能以太网PHY芯片，集成诊断与节能功能

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LAN8742A数据手册是一份详细的技术文档，由Microchip Technology Inc.在2013年至2015年期间发布。该芯片是一款高度集成的以太网物理层收发器(PHY)，专为各种应用设计，包括但不限于家庭娱乐系统、网络设备、工业测试仪器以及嵌入式通信解决方案。以下是关键特点和优势： 1. **单芯片解决方案**：LAN8742A在一个小巧的24引脚VQFN封装（4x4x0.9毫米高度）内集成了所有必要的功能，提供了紧凑且高效的设计。 2. **诊断支持**：内置的功能有助于检测和诊断网络连接问题，提高了系统的稳定性和可靠性。 3. **唤醒通过局域网(WoL)**：支持WOL功能，允许设备在接收到特定网络信号时自动从待机模式唤醒，节省能源并提高效率。 4. **灵活电源管理**：采用了先进的flexPWR技术，提供一个可变输入电压范围（+1.8V至+3.3V），并且内置了一个1.2V可禁用的稳压器，为不同应用场景提供了电源适应性。 5. **HP Auto-MDIX支持**：自动检测和兼容MDIX（即自动双工/自适应MDI-X）功能，简化了电缆配置，减少了布线复杂性。 6. **广泛的应用领域**：该芯片适用于各种广泛的终端设备，如机顶盒、网络打印机和服务器、游戏机、无线接入点、数字电视、媒体适配器等，满足不同行业的通信需求。 7. **高性能标准兼容**：符合IEEE 802.3/802.3u（快速以太网）和ISO 802-3/IEEE 802.3（10BASE-T）标准，确保了高速、可靠的数据传输。 8. **内置功能**：提供回环模式、自动协商、自动极性检测和校正等功能，降低了系统设计的复杂性和错误率。 9. **PoE支持**：对于需要供电的设备，该芯片也支持PoE（Power over Ethernet），通过以太网线传输电力和数据，便于部署和维护。 LAN8742A数据手册介绍了这款高性能以太网PHY的重要特性和优势，对于寻求高效、灵活且易于集成的网络解决方案的工程师来说，是十分有价值的参考资料。它能够简化设计流程，提高产品的市场竞争力，是现代网络设备开发中的重要组件。

LAN8742A/LAN8742Ai

DS00001989A-page 16  2013-2015 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

This chapter provides functional descriptions of the various device features. These features have been categorized into

the following sections:

• Transceiver

• Auto-Negotiation

• HP Auto-MDIX Support

• MAC Interface

• Serial Management Interface (SMI)

• Interrupt Management

• Configuration Straps

• Miscellaneous Functions

• Application Diagrams

3.1 Transceiver

3.1.1 100BASE-TX TRANSMIT

The 100BASE-TX transmit data path is shown in Figure 3-1. Each major block is explained in the following subsections.

3.1.1.1 100BASE-TX Transmit Data Across the RMII Interface

The MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data is

latched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50 MHz data.

3.1.1.2 4B/5B Encoding

The transmit data passes from the RMII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to

5-bit symbols (known as “code-groups”) according to Table 3-1. Each 4-bit data-nibble is mapped to 16 of the 32 pos-

sible code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The

remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is

/I/, a transmit error code-group is /H/, etc.

FIGURE 3-1: 100BASE-TX TRANSMIT DATA PATH

MAC

Driver

MLT-3

Converter

NRZI

Converter

4B/5B

Encoder

CAT-5RJ45

25 MHz by

5 bits

NRZI

MLT-3MLT-3

MLT-3

Scrambler

and PISO

RMII

25 MHz

by 4 bits

Ext Ref_CLK

PLL

RMII 50 MHz by 2 bits

MLT-3

Magnetics

125 Mbps Serial

LAN8742A/LAN8742Ai

DS00001989A-page 18  2013-2015 Microchip Technology Inc.

3.1.1.3 Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band

peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire

channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being

radiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiver

applications, such as repeaters or switches, each transceiver will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

3.1.1.4 NRZI and MLT-3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125 MHz NRZI

data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a

code bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.1.1.5 100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP and

TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass

through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100 Ω

impedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.1.1.6 100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the

100BASE-TX transmitter.

3.1.2 100BASE-TX RECEIVE

The 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.

FIGURE 3-2: 100BASE-TX RECEIVE DATA PATH

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics CAT-5RJ45

PLL

RMII 50 MHz by 2 bits

25 MHz by

5 bits

NRZI

MLT-3MLT-3 MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

RMII

25 MHz

by 4 bits

Ext Ref_CLK

 2013-2015 Microchip Technology Inc. DS00001989A-page 19

LAN8742A/LAN8742Ai

3.1.2.1 100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC

samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates

6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels

such that the full dynamic range of the ADC can be used.

3.1.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-

tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer

can restore the signal for any good-quality CAT-5 cable between 1 m and 100 m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-

lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)

on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and can

receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing unit of the DSP,

selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to

extract the serial data from the received signal.

3.1.2.3 NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an

NRZI data stream.

3.1.2.4 Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel

Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once

synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols

within a window of 4000 bytes (40 µs). This window ensures that a maximum packet size of 1514 bytes, allowed by the

IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,

receive operation is aborted and the descrambler re-starts the synchronization process.

3.1.2.5 Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)

pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of

frame.

3.1.2.6 5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-

sented on the RXD[1:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC pre-

amble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is

available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of

Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert

the carrier sense and receive data valid signals.

Note: These symbols are not translated into data.

LAN8742A/LAN8742Ai

DS00001989A-page 20  2013-2015 Microchip Technology Inc.

3.1.2.7 Receive Data Valid Signal

The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the

RXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD

is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure

or SIGDET becomes false.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII

mode).

3.1.2.8 Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary

data is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being

decoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that the

Valid Data signal is not yet asserted when the bad SSD error occurs.

3.1.2.9 100M Receive Data Across the RMII Interface

The 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50 MHz.

The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK).

3.1.3 10BASE-T TRANSMIT

Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the

MII at a rate of 2.5 MHz and converts them to a 10 Mbps serial data stream. The data stream is then Manchester-

encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

• MII (digital)

• TX 10M (digital)

• 10M Transmitter (analog)

• 10M PLL (analog)

3.1.3.1 10M Transmit Data Across the MII/RMII Interface

The MAC controller drives the transmit data onto the TXD bus. TXD[1:0] shall transition synchronously with respect to

REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be “00” to

indicate idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved for

out-of-band signaling (to be defined). Values other than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by

the device.TXD[1:0] shall provide valid data for each REF_CLK period while TXEN is asserted.

In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the trans-

mitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during

this time. The transceiver also supports the SQE (Heartbeat) signal.

FIGURE 3-3: RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS

5D5 data data data data

RXD

RX_DV

RX_CLK

5D5

data data data data

CLEAR-TEXT

5JK

5 55

Idle

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