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Freescale MPC5607B 微控制器参考手册
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"MPC5607B是Freescale Semiconductor公司生产的一款微控制器,相关的数据手册(datasheet)包括MPC5607B Reference Manual Addendum (MPC5607BRMAD) 和 MPC5607B Reference Manual (MPC5607BRM),版本分别为Rev.1和Rev.7.2,发布于2012年。这些文档主要由Microcontroller Solutions Group编写,提供关于MPC5607B微控制器的详细信息和修正内容。文档中包含了错误修正、修订历史和最新的更新内容,用户可以访问Freescale Semiconductor的官方网站获取最新的信息。"
MPC5607B是一款基于Power Architecture技术的微控制器,它集成了多种功能模块,适用于汽车电子、工业控制等领域的应用。以下是对这款微控制器的关键知识点的详细说明:
1. **架构**:MPC5607B基于Eclipse内核,这是一款高性能、低功耗的32位处理器,支持嵌入式实时操作系统。
2. **内存系统**:该微控制器可能包含闪存、SRAM以及寄存器等内存组件,用于存储程序代码、数据和工作寄存器。
3. **外设接口**:MPC5607B可能配备了各种外设接口,如CAN(Controller Area Network)总线用于汽车通信,SPI、I²C和UART用于串行通信,以及GPIO(General Purpose Input/Output)用于控制外部设备。
4. **模拟功能**:考虑到在汽车电子中的应用,它可能具有ADC(Analog-to-Digital Converter)和DAC(Digital-to-Analog Converter),用于处理模拟信号。
5. **定时器和计数器**:MPC5607B通常会包含多个定时器和计数器,用于实现精确的时间控制和事件测量。
6. **电源管理**:为了适应不同应用需求和节能,微控制器可能具备灵活的电源管理模式,如睡眠模式、待机模式等。
7. **安全特性**:在汽车电子领域,安全性能至关重要。MPC5607B可能集成了一些安全特性,如故障检测、看门狗定时器和加密单元,以确保系统的稳定性和安全性。
8. **开发工具和支持**:与MPC5607B相关的开发工具可能包括IDE(Integrated Development Environment)、编译器、调试器和仿真器,以帮助开发者进行软件开发和系统调试。
9. **固件升级**:微控制器可能支持通过CAN或其他通信协议进行固件升级,以实现远程维护和功能扩展。
10. **修订历史和更新**:文档的修订历史反映了产品的发展和改进过程,用户应关注这些更新以获取最新特性和修复的问题。
MPC5607B是一款综合了强大处理能力、多种接口和模拟功能的微控制器,适用于需要高性能、低功耗解决方案的复杂嵌入式系统。开发者可以通过其详细的数据手册和参考手册了解其全部功能和正确使用方法。
MPC5607B Microcontroller Reference Manual, Rev. 7.1
Freescale Semiconductor 5
6.5.2 Functional description ..................................................................................................118
6.5.3 Register description ......................................................................................................119
6.6 Fast internal RC oscillator (FIRC) digital interface ......................................................................119
6.6.1 Introduction ..................................................................................................................119
6.6.2 Functional description ..................................................................................................120
6.6.3 Register description ......................................................................................................121
6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................121
6.7.1 Introduction ..................................................................................................................121
6.7.2 Overview ......................................................................................................................122
6.7.3 Features .........................................................................................................................122
6.7.4 Memory map ................................................................................................................123
6.7.5 Register description ......................................................................................................123
6.7.6 Functional description ..................................................................................................126
6.7.7 Recommendations ........................................................................................................129
6.8 Clock monitor unit (CMU) ............................................................................................................129
6.8.1 Introduction ..................................................................................................................129
6.8.2 Main features ................................................................................................................130
6.8.3 Block diagram ..............................................................................................................130
6.8.4 Functional description ..................................................................................................131
6.8.5 Memory map and register description ..........................................................................133
Chapter 7
Clock Generation Module (MC_CGM)
7.1 Overview .......................................................................................................................................139
7.2 Features .........................................................................................................................................140
7.3 Modes of operation ........................................................................................................................141
7.3.1 Normal and reset modes of operation ...........................................................................141
7.4 External signal description ............................................................................................................141
7.5 Memory map and register definition .............................................................................................141
7.5.1 Register descriptions ....................................................................................................145
7.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................146
7.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................147
7.6 Functional Description ..................................................................................................................149
7.6.1 System Clock Generation .............................................................................................149
7.6.2 Output Clock Multiplexing ...........................................................................................150
7.6.3 Output Clock Division Selection ..................................................................................151
Chapter 8
Mode Entry Module (MC_ME)
8.1 Overview .......................................................................................................................................153
8.1.1 Features .........................................................................................................................155
8.1.2 Modes of Operation ......................................................................................................155
8.2 External Signal Description ..........................................................................................................156
8.3 Memory Map and Register Definition ..........................................................................................156
8.3.1 Register Description .....................................................................................................165
MPC5607B Microcontroller Reference Manual, Rev. 7.1
6 Freescale Semiconductor
8.4 Functional Description ..................................................................................................................187
8.4.1 Mode Transition Request ..............................................................................................187
8.4.2 Modes Details ...............................................................................................................188
8.4.3 Mode transition process ................................................................................................193
8.4.4 Protection of Mode Configuration Registers ................................................................203
8.4.5 Mode Transition Interrupts ...........................................................................................203
8.4.6 Peripheral Clock Gating ...............................................................................................205
8.4.7 Application Example ....................................................................................................206
Chapter 9
Reset Generation Module (MC_RGM)
9.1 Introduction ...................................................................................................................................209
9.1.1 Overview ......................................................................................................................209
9.1.2 Features .........................................................................................................................210
9.1.3 Modes of operation .......................................................................................................211
9.2 External Signal Description ..........................................................................................................212
9.3 Memory Map and Register Definition ..........................................................................................212
9.3.1 Register descriptions ....................................................................................................215
9.4 Functional description ...................................................................................................................225
9.4.1 Reset State Machine .....................................................................................................225
9.4.2 Destructive resets ..........................................................................................................229
9.4.3 External reset ................................................................................................................230
9.4.4 Functional resets ...........................................................................................................230
9.4.5 STANDBY entry sequence ...........................................................................................231
9.4.6 Alternate event generation ............................................................................................231
9.4.7 Boot mode capturing ....................................................................................................232
Chapter 10
Power Control Unit (MC_PCU)
10.1 Introduction ...................................................................................................................................233
10.1.1 Overview ......................................................................................................................233
10.1.2 Features .........................................................................................................................234
10.1.3 Modes of operation .......................................................................................................235
10.2 External signal description ............................................................................................................235
10.3 Memory map and register definition .............................................................................................235
10.3.1 Register descriptions ....................................................................................................237
10.4 Functional description ...................................................................................................................240
10.4.1 General .........................................................................................................................240
10.4.2 Reset / Power-On Reset ................................................................................................240
10.4.3 MC_PCU configuration ................................................................................................240
10.4.4 Mode transitions ...........................................................................................................241
10.5 Initialization information ...............................................................................................................243
10.6 Application information ................................................................................................................244
10.6.1 STANDBY Mode Considerations ................................................................................244
MPC5607B Microcontroller Reference Manual, Rev. 7.1
Freescale Semiconductor 7
Chapter 11
Voltage Regulators and Power Supplies
11.1 Voltage regulators ..........................................................................................................................245
11.1.1 High power regulator (HPREG) ...................................................................................245
11.1.2 Low power regulator (LPREG) ....................................................................................245
11.1.3 Ultra low power regulator (ULPREG) .........................................................................246
11.1.4 LVDs and POR .............................................................................................................246
11.1.5 VREG digital interface .................................................................................................246
11.1.6 Register description ......................................................................................................247
11.2 Power supply strategy ...................................................................................................................247
11.3 Power domain organization ...........................................................................................................248
Chapter 12
Wakeup Unit (WKPU)
12.1 Overview .......................................................................................................................................251
12.2 Features .........................................................................................................................................253
12.3 External signal description ............................................................................................................254
12.4 Memory map and register description ...........................................................................................254
12.4.1 Memory map ................................................................................................................254
12.4.2 NMI Status Flag Register (NSR) ..................................................................................255
12.4.3 NMI Configuration Register (NCR) .............................................................................256
12.4.4 Wakeup/Interrupt Status Flag Register (WISR) ...........................................................257
12.4.5 Interrupt Request Enable Register (IRER) ...................................................................257
12.4.6 Wakeup Request Enable Register (WRER) ..................................................................258
12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................258
12.4.8 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................259
12.4.9 Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................259
12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................260
12.5 Functional description ...................................................................................................................260
12.5.1 General .........................................................................................................................260
12.5.2 Non-maskable interrupts ..............................................................................................261
12.5.3 External wakeups/interrupts .........................................................................................262
12.5.4 On-chip wakeups ..........................................................................................................264
Chapter 13
Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.1 Overview .......................................................................................................................................265
13.2 Features .........................................................................................................................................265
13.3 Device-specific information ..........................................................................................................267
13.4 Modes of operation ........................................................................................................................267
13.4.1 Functional mode ...........................................................................................................267
13.4.2 Debug mode ..................................................................................................................268
13.5 Register descriptions .....................................................................................................................268
13.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................268
13.5.2 RTC Control Register (RTCC) .....................................................................................269
MPC5607B Microcontroller Reference Manual, Rev. 7.1
8 Freescale Semiconductor
13.5.3 RTC Status Register (RTCS) ........................................................................................271
13.5.4 RTC Counter Register (RTCCNT) ...............................................................................272
13.6 RTC functional description ...........................................................................................................272
13.7 API functional description ............................................................................................................273
Chapter 14
CAN Sampler
14.1 Introduction ...................................................................................................................................275
14.2 Main features .................................................................................................................................275
14.3 Memory map and register description ...........................................................................................276
14.3.1 Control Register (CR) ...................................................................................................276
14.3.2 CAN Sampler Sample Registers 0–11 ..........................................................................277
14.4 Functional description ...................................................................................................................277
14.4.1 Enabling/disabling the CAN sampler ...........................................................................278
14.4.2 Selecting the Rx port ....................................................................................................278
14.4.3 Baudrate generation ......................................................................................................279
Chapter 15
e200z0h Core
15.1 Overview .......................................................................................................................................283
15.2 Microarchitecture summary ..........................................................................................................283
15.3 Block diagram ...............................................................................................................................285
15.4 Features .........................................................................................................................................285
15.4.1 Instruction unit features ................................................................................................286
15.4.2 Integer unit features ......................................................................................................286
15.4.3 Load/Store unit features ...............................................................................................287
15.4.4 e200z0h system bus features ........................................................................................287
15.4.5 Nexus 2+ features .........................................................................................................287
15.5 Core registers and programmer’s model .......................................................................................288
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Device-specific features ................................................................................................................291
16.2 Introduction ...................................................................................................................................291
16.2.1 Features .........................................................................................................................292
16.3 Memory map and register definition .............................................................................................293
16.3.1 Memory map ................................................................................................................293
16.3.2 Register descriptions ....................................................................................................295
16.4 Functional description ...................................................................................................................316
16.4.1 eDMA basic data flow ..................................................................................................318
16.5 Initialization / application information ..........................................................................................321
16.5.1 eDMA initialization ......................................................................................................321
16.5.2 DMA programming errors ............................................................................................323
16.5.3 DMA request assignments ............................................................................................324
16.5.4 DMA arbitration mode considerations .........................................................................324
MPC5607B Microcontroller Reference Manual, Rev. 7.1
Freescale Semiconductor 9
16.5.5 DMA transfer ................................................................................................................325
16.5.6 TCD status ....................................................................................................................328
16.5.7 Channel linking ............................................................................................................329
16.5.8 Dynamic programming .................................................................................................330
Chapter 17
eDMA Channel Multiplexer (DMA_MUX)
17.1 Introduction ...................................................................................................................................333
17.2 Features .........................................................................................................................................333
17.3 Modes of operation ........................................................................................................................334
17.4 External signal description ............................................................................................................334
17.5 Memory map and register definition .............................................................................................334
17.5.1 Channel configuration registers (CHCONFIGn) ..........................................................335
17.6 DMA_MUX inputs .......................................................................................................................336
17.6.1 DMA_MUX peripheral sources ...................................................................................336
17.6.2 DMA_MUX periodic trigger inputs .............................................................................338
17.7 Functional description ...................................................................................................................338
17.7.1 eDMA channels with periodic triggering capability ....................................................338
17.7.2 eDMA channels with no triggering capability .............................................................340
17.8 Initialization/Application information ...........................................................................................341
17.8.1 Reset .............................................................................................................................341
17.8.2 Enabling and configuring sources ................................................................................341
Chapter 18
Interrupt Controller (INTC)
18.1 Introduction ...................................................................................................................................345
18.2 Features .........................................................................................................................................345
18.3 Block diagram ...............................................................................................................................347
18.4 Modes of operation ........................................................................................................................348
18.4.1 Normal mode ................................................................................................................348
18.5 Memory map and register description ...........................................................................................349
18.5.1 Module memory map ...................................................................................................349
18.5.2 Register description ......................................................................................................350
18.6 Functional description ...................................................................................................................357
18.6.1 Interrupt request sources ...............................................................................................365
18.6.2 Priority management ....................................................................................................366
18.6.3 Handshaking with processor .........................................................................................368
18.7 Initialization/application information ............................................................................................370
18.7.1 Initialization flow .........................................................................................................370
18.7.2 Interrupt exception handler ...........................................................................................370
18.7.3 ISR, RTOS, and task hierarchy .....................................................................................372
18.7.4 Order of execution ........................................................................................................373
18.7.5 Priority ceiling protocol ................................................................................................374
18.7.6 Selecting priorities according to request rates and deadlines .......................................374
18.7.7 Software configurable interrupt requests ......................................................................375
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