PCI Local Bus 3.0：分时复用与即插即用技术详解

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PCI Local Bus Specification Revision 3.0 是一项于2004年2月3日发布的标准，它定义了PCI（Peripheral Component Interconnect局部总线）的最新规范，旨在改进早期版本的功能和性能。PCI总线是一种广泛应用于个人计算机内部的高速接口，它连接处理器、扩展卡和其他系统组件，提供了即插即用（Plug and Play）的能力，这意味着新设备接入后无需重新配置即可自动识别并运行。该版本的主要特性包括： 1. **地址与数据总线复用**：PCI总线采用分时复用技术，地址总线和数据总线在不同时间周期交替使用，这既节省了硬件成本（通过减少接插件引脚），又支持高效的数据传输。这种设计允许在短时间内连续传输大量数据，提高了系统的整体性能。 2. **支持500MHz和66MHz工作模式**：随着规格升级，PCI 3.0支持更高的频率，比如66MHz，增强了数据传输速率，从而满足了对更快处理速度和带宽的需求。 3. **修订历史**：从最初的1.0版到3.0版，每次修订都反映了对先前版本的改进和错误修正，包括集成新的功能、澄清技术细节、解决错误和适应新的硬件需求。例如，2.3版移除了对5.0伏特键控系统板连接器的支持，并将扩展ROM描述转移到PCI固件规范中。 4. **责任声明**：PCI-SIG（PCI Special Interest Group）明确表示，他们不对文档的使用或其中信息的准确性负责，也不承诺更新文档内容，用户应直接联系PCI-SIG获取最新的规范版本。 5. **获取支持**：对于任何关于规范的问题或加入PCI-SIG的兴趣，用户可以访问PCI-SIG的网站（http://www.pcisig.com）或发送电子邮件至administration@pcisi进行咨询。 PCI Local Bus Specification Revision 3.0是现代计算机架构中的重要组成部分，它通过优化总线设计和增强功能，确保了系统的可靠性和兼容性，为计算机硬件的升级和扩展提供了坚实的基础。

PCI LOCAL BUS SPECIFICATION, REV. 3.0

1.3. PCI Local Bus Applications

The PCI Local Bus has been defined with the primary goal of establishing an industry

standard, high performance local bus architecture that offers low cost and allows

differentiation. While the primary focus is on enabling new price-performance points in

today's systems, it is important that a new standard also accommodates future system

requirements and be applicable across multiple platforms and architectures. Figure 1-1

shows the multiple dimensions of the PCI Local Bus.

Servers

Mobile

High End

Desktops

Low, Mid-

Range

Desktop

Auto

Configuration

64-bit Upgrade

Path

PCI 33

PCI 66

PCI-X 66

PCI-X 133

PCI-X 266

PCI-X 533

PCI Express

A-0151

Figure 1-1: PCI Local Bus Applications

While the initial focus of local bus applications was on low to high end desktop systems, the

PCI Local Bus also comprehends the requirements from mobile applications up through

servers. The PCI Local Bus specifies 3.3 volt signaling requirements.

The PCI component and add-in card interface is processor independent, enabling an

efficient transition to future processor generations and use with multiple processor

architectures. Processor independence allows the PCI Local Bus to be optimized for I/O

functions, enables concurrent operation of the local bus with the processor/memory

subsystem, and accommodates multiple high performance peripherals in addition to graphics

(motion video, LAN, SCSI, FDDI, hard disk drives, etc.). Movement to enhanced video

and multimedia displays (i.e., HDTV and 3D graphics) and other high bandwidth I/O will

continue to increase local bus bandwidth requirements. A transparent 64-bit extension of

the 32-bit data and address buses is defined, doubling the bus bandwidth and offering

forward and backward compatibility of 32-bit and 64-bit PCI Local Bus peripherals. A

forward and backward compatible PCI-X specification (see the PCI-X Addendum to the PCI

Local Bus Specification) is also defined, increasing the bandwidth capabilities of the 33 MHz

definition by a factor of four.

The PCI Local Bus standard offers additional benefits to the users of PCI based systems.

Configuration registers are specified for PCI components and add-in cards. A system with

embedded auto configuration software offers true ease-of-use for the system user by

automatically configuring PCI add-in cards at power on.

PCI LOCAL BUS SPECIFICATION, REV. 3.0

1.5. PCI Local Bus Features and Benefits

The PCI Local Bus was specified to establish a high performance local bus standard for

several generations of products. The PCI specification provides a selection of features that

can achieve multiple price-performance points and can enable functions that allow

differentiation at the system and component level. Features are categorized by benefit as

follows:

High Performance

 Transparent upgrade from 32-bit data path at 33 MHz

(132 MB/s peak) to 64-bit data path at 33 MHz

(264 MB/s peak), from 32-bit data path at 66 MHz (264 MB/s

peak) to 64-bit data path at 66 MHz (532 MB/s peak), and from

32-bit data path at 133 MHz (532 MB/s peak) to 64-bit data path

at 133 MHz (1064 MB/s peak).

 Variable length linear and cacheline wrap mode bursting for both

read and writes improves write dependent graphics performance.

 Low latency random accesses (60-ns write access latency for

33 MHz PCI to 30-ns for 133 MHz PCI-X to slave registers

from master parked on bus).

 Capable of full concurrency with processor/memory subsystem.

 Synchronous bus with operation up to 33 MHz, 66 MHz, or

133 MHz.

 Hidden (overlapped) central arbitration.

Low Cost

 Optimized for direct silicon (component) interconnection; i.e.,

no glue logic. Electrical/driver (i.e., total load) and frequency

specifications are met with standard ASIC technologies and

other typical processes.

 Multiplexed architecture reduces pin count (47 signals for target;

49 for master) and package size of PCI components or provides

for additional functions to be built into a particular package size.

Ease of Use

 Enables full auto configuration support of PCI Local Bus add-in

cards and components. PCI devices contain registers with the

device information required for configuration.

Longevity

 Processor independent. Supports multiple families of processors

as well as future generations of processors (by bridges or by

direct integration).

 Support for 64-bit addressing.

 The 3.3-volt system signaling environment is specified with the

universal add-in card providing backward compatibility to 5-volt

signaling systems.

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