DDR3L SDRAM规格详解 - MT41K系列

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"MT41K512M16HA IT.pdf 是一款DDR3L SDRAM内存芯片，由Micron Technology生产。该芯片适用于低电压应用，具有1.35V的工作电压，并且与1.5V DDR3 SDRAM设备兼容。其特点包括低功耗、多种可编程参数以及多种工作模式，如自我刷新和自动自我刷新功能，适用于各种系统需求。" DDR3L SDRAM是DDR3 SDRAM的低电压版本，专为减少功耗而设计。MT41K512M16HA IT芯片提供了不同的存储密度选项，如2Gbit（MT41K2G4），1Gbit（MT41K1G8）和512Mbit（MT41K512M16）。这些芯片分别基于256M x 4, 128M x 8 和64M x 16的组织结构，拥有8个内部银行，这允许并行访问，提高数据处理速度。该芯片的关键特性包括： 1. **低电压操作**：VDD和VDDQ电源引脚的工作电压为1.35V，但同时也支持1.5V兼容模式，以确保向后兼容性。 2. **双向差分数据 strobe**：采用差分双向数据 strobe (DQS)信号，提高数据传输的准确性和稳定性。 3. **8n位预取架构**：这种架构提高了数据传输速率，因为它可以在每个时钟周期内处理更多位的数据。 4. **差分时钟输入**：包括CK和CK#，确保时钟信号的清晰传输。 5. **8个内部银行**：多银行设计增加了并发访问的可能性，从而提升内存性能。 6. **可编程参数**：包括CAS读取延迟(CL)，附加读取延迟(AL)，写入CAS延迟(CWL)，以及固定突发长度(BL)为8和突发切分(BC)为4，可通过模式寄存器集(MRS)进行配置。 7. **选择性BC4或BL8**：在运行过程中动态切换突发长度，提供了更大的灵活性。 8. **自我刷新模式**：在低功耗状态下保持数据完整性，适用于电源受限的应用。 9. **温度补偿**：支持0°C至+95°C的工作温度范围，有不同的刷新要求以适应不同温度条件。 10. **自刷新温度设置（SRT）**：允许根据系统环境温度自动调整刷新策略。 11. **自动自刷新（ASR）**：进一步降低功耗，自动执行刷新操作。 12. **写级别校准**：优化输出驱动以确保数据传输的一致性。 13. **多功能寄存器**：提供额外的控制和配置选项。 14. **输出驱动校准**：确保信号的精确传输，尤其是在高速操作中。 MT41K512M16HA IT芯片是现代计算和嵌入式系统中的关键组件，其低电压特性和高度可配置性使其成为高效能、低能耗应用的理想选择，例如笔记本电脑、服务器、路由器和各种嵌入式系统。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A15

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. C 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Com-

mand section.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. C 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Com-

mand section.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle),or active power-down (row active in any bank). CKE is synchronous for power-

down entry and exit and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF

REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-

vides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a

write access. Although the LDM ball is input-only, the LDM loading is

designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,

LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,

and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for

the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is

referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. C 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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