STM32 Cortex-M0+编程手册：性能与特性详解

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本文档是关于Cortex-M0+处理器编程手册，适用于STM32L0、STM32G0、STM32WL和STM32WB系列微控制器。Cortex-M0+是一款高性能的32位处理器，特别设计用于嵌入式系统，其主要特点包括： 1. **卓越的处理性能与快速中断处理**：Cortex-M0+提供了出色的处理器性能，确保了高效的执行速度，同时具备快速中断响应能力，这对于实时应用至关重要。 2. **增强的系统调试功能**：手册详述了丰富的断点选项，使得软件开发者可以方便地进行系统级调试，有助于诊断和优化代码。 3. **高效处理器核心和内存**：该处理器的核心架构经过精心设计，旨在提高代码执行效率，同时支持高效的数据存储和处理。 4. **极低功耗**：Cortex-M0+集成了多种低功耗模式，如睡眠模式，以满足电池供电设备对能源管理的需求，延长设备待机时间。 5. **平台安全**：为了保护知识产权和应用程序安全，手册涉及平台的安全特性，包括可能的加密和防护机制。文档结构包括： - **关于此文档**：介绍文档的目的、排版规则和缩写列表。 - **Cortex-M0+处理器和核心外设**：详细解释处理器的系统接口和集成的外围组件，这些是理解和开发应用的基础。 - **系统级接口**：阐述处理器与其他系统部件（如外设、内存）的交互方式，以及接口规范。 - **内核架构与寄存器**：描述处理器的内核架构，以及关键寄存器的功能和使用方法。 - **编程模型和指令集**：提供编程指导，帮助开发者理解处理器的工作原理和编程语言特性。 - **电源管理和低功耗模式**：详细介绍如何在不同功耗模式下操作，以优化能效。 - **异常和中断处理**：讲解中断管理机制，如何设计中断服务程序(ISRs)以提高系统的响应速度。 - **调试工具和支持**：介绍可用的调试工具和调试策略，以及如何利用这些工具进行调试工作。此文档是针对Cortex-M0+微控制器开发人员的一份全面指南，涵盖了从处理器核心到应用层面的各个方面，对于深入理解和有效利用这一处理器平台非常有价值。

Cortex-M0+ processor PM0223

16/110 PM0223 Rev 5

See The condition flags on page 43 for more information about the APSR negative, zero,

carry or borrow, and overflow flags.

Interrupt Program Status Register

The IPSR contains the exception number of the current Interrupt Service Routine (ISR). See

the register summary in

Table 2 on page 13 for its attributes. The bit assignments are:

Execution Program Status Register

The EPSR contains the Thumb state bit.

See the register summary in Table 2 on page 13 for the EPSR attributes. The bit

assignments are:

[28] V Overflow flag.

[27:0] - Reserved.

Table 5. IPSR bit assignments

Bits Name Function

[31:6] - Reserved

[5:0] Exception number This is the number of the current exception:

0 = Thread mode.

1 = Reserved.

2 = NMI.

3 = HardFault.

4-10 = Reserved.

11 = SVCall.

12, 13 = Reserved.

14 = PendSV.

15 = SysTick | Reserved.

16 = IRQ0.

47 = IRQ31.

48-63 = Reserved.

see Exception types on page 26 for more information.

Table 4. APSR bit assignment (continued)

Bits Name Description

PM0223 Rev 5 17/110

PM0223 Cortex-M0+ processor

Attempts by application software to read the EPSR directly using the MRS instruction always

return zero. Attempts to write the EPSR using the

MRS instruction are ignored. Fault

handlers can examine the EPSR value in the stacked PSR to determine the cause of the

fault. See

Exception entry and return on page 30. The following can clear the T bit to 0:

• Instructions BLX, BX and POP{PC}.

• Restoration from the stacked xPSR value on an exception return.

• Bit[0] of the vector value on an exception entry.

Attempting to execute instructions when the T bit is 0 results in a HardFault or Lockup. See

2.4.1: Lockup on page 33 for more information.

Interruptible-restartable instructions

The interruptible-restartable instructions are LDM and STM, PUSH, POP, and MULS. When

an interrupt occurs during the execution of one of these instructions, the processor

abandons execution of the instruction. After servicing the interrupt, the processor restarts

execution of the instruction from the beginning.

Exception mask register

The exception mask register disables the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks or code sequences requiring

atomicity.

To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS

instruction, to change the value of PRIMASK.

3.7.6: MRS on page 74, 3.7.7: MSR on

page 75, and 3.7.2: CPS on page 70 for more information.

Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. See

the register summary in

Table 2 on page 13 for its attributes. The bit assignments are:

Table 6. EPSR bit assignments

Bits Name Function

[31:25] - Reserved.

[24] T Thumb state bit.

[23:0] - Reserved.

Table 7. PRIMASK register bit assignments

Bits Name Function

[31:1] - Reserved.

[0] PM Prioritizable interrupt mask:

0 = No effect.

1 = Prevents the activation of all exceptions with configurable

priority.

PM0223 Rev 5 19/110

PM0223 Cortex-M0+ processor

Handler mode to handle all exceptions except for reset. See Exception entry on page 31

and Exception return on page 32 for more information.

The NVIC registers control interrupt handling. See 4.2: Nested vectored interrupt controller

on page 82 for more information.

2.1.5 Data types

The processor:

• Supports the following data types:

– 32-bit words.

– 16-bit halfwords.

–8-bit bytes.

• Manages all data memory accesses as little-endian or big-endian. Instruction memory

and Private Peripheral Bus (PPB) accesses are always little-endian. See 2.2.1:

Memory regions, types and attributes on page 21 for more information.

2.1.6 The Cortex Microcontroller Software Interface Standard

Arm

provides the Cortex Microcontroller Software Interface Standard (CMSIS) for

programming Cortex-M0+ microcontrollers. The CMSIS is an integrated part of the device

driver library. For a Cortex-M0+ microcontroller system, CMSIS defines:

• A common way to:

– Access peripheral registers.

– Define exception vectors.

• The names of:

– The registers of the core peripherals.

– The core exception vectors.

• A device-independent interface for RTOS kernels.

The CMSIS includes address definitions and data structures for the core peripherals in the

Cortex-M0+ processor. It also includes optional interfaces for middleware components

comprising a TCP/IP stack and a Flash file system.

The CMSIS simplifies software development by enabling the reuse of template code, and

the combination of CMSIS-compliant software components from various middleware

vendors. Software vendors can expand the CMSIS to include their peripheral definitions and

access functions for those peripherals.

This document includes the register names defined by the CMSIS, and gives short

descriptions of the CMSIS functions that address the processor core and the core

peripherals.

Note: This document uses the register short names defined by the CMSIS. In a few cases these

differ from the architectural short names that might be used in other documents.

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