安森美500W全球快门CMOS图像传感器详细规格

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安森美半导体公司发布的500W像素全球快门CMOS图像传感器产品系列，型号包括NOIP1SN5000A/D、NOIP1SN5000A和NOIP1SN2000A，特别针对的是PYTHON 5.0/2.0百万像素的应用需求。该传感器具有以下几个关键特性： 1. 高分辨率：500万像素版本提供了2592x2048的活跃像素，而200万像素版本则有1920x1200像素，满足了不同应用场景对清晰度的需求。 2. 低噪声全球快门：采用4.8x4.8毫米的像素，内置在像素内的电荷存储单元（CDS）有助于降低噪声，确保图像质量的稳定。 3. 多种色彩选项：支持单色（SN）、彩色（SE）和近红外（FN）三种模式，适用于不同的光谱范围应用。 4. 高帧率模式：通过零旋转模式（Zero ROT Mode），传感器可以在全分辨率或高清模式下实现高达100/85帧每秒（fps）（对于5MP，非零旋转时略有降低）的高速拍摄，2MP模式下的帧率则分别达到230/180 fps。 5. 高性能接口：内置10位模拟到数字转换器（ADC），支持8位或10位输出模式，并提供8个低电压差分信号（LVDS）高速串行输出，方便数据传输。 6. 功能多样性：支持随机可编程区域兴趣（ROI），允许用户根据需要调整采集范围。读取方式包括流水线和触发式全局快门，以及LVDS通道复用。 7. 内置校准功能：提供在芯片上的固定图案噪声（FPN）校正，提高了图像一致性。还支持串行外围接口（SPI）进行灵活通信。 8. 先进的控制功能：包括自动曝光控制（AEC）、相位锁定环（PLL）以及高动态范围（HDR）处理，确保在各种光照条件下都能获得准确的图像。 9. 双电源设计：兼容3.3伏和1.8伏电源，增加了系统的灵活性和功耗管理能力。这款安森美500W传感器集成了多种高级功能，适用于工业成像、无人机航拍、安防监控等领域，能够提供出色的图像质量和高帧率捕捉能力，是现代图像处理系统中的关键组件。

NOIP1SN5000A, NOIP1SN2000A

www.onsemi.com

Non−Zero and Zero Row Overhead Time (ROT) Modes

In pipelined global shutter mode, the integration and

readout are done in parallel. Images are continuously read

out and integration of frame N is ongoing during readout of

the previous frame N−1. The readout of every frame starts

with a Frame Overhead Time (FOT), during which the

analog value of the pixel diode is transferred to the pixel

memory element. After the FOT, the sensor is read out line

by line and the readout of each line is preceded by a Row

Overhead Time (ROT) as shown in Figure 14.

In Reduced/Zero ROT operation mode (refer to

Figure 15), the row blanking and kernel readout occur in

parallel. This mode is called reduced ROT as a part of the

ROT is done while the image row is readout. The actual ROT

can thus be longer, however the perceived ROT will be

shorter (‘overhead’ spent per line is reduced).

This operation mode can be used for two reasons:

• Reduced total line time.

• Lower power due to reduced clock−rate.

Figure 14. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with

Non−Zero ROT Readout.

ROT

ys+1

ROT

Readout

Valid Data

FOT

()

Readout

Figure 15. Integration and Readout Sequence of the Sensor operating in Pipelined Global Shutter Mode with

Zero ROT Readout.

ROT

(blanked out)

ROT

Readout

ys+1

ROT

Readout

ye−1

ROT

Readout

dummy

Valid Data

FOT

()

NOIP1SN5000A, NOIP1SN2000A

www.onsemi.com

Sensor States

Low Power Standby

In low power standby state, all power supplies are on, but

internally every block is disabled. No internal clock is

running (PLL / LVDS clock receiver is disabled).

All register settings are set to their default values (see

Table 35).

Only a subset of the SPI registers is active for read/write

in order to be able to configure clock settings and leave the

low power standby state. The only SPI registers that should

be touched are the ones required for the ‘Enable Clock

Management’ action described in Enable Clock

Management − Part 1 on page 16

Standby (1)

In standby state, the PLL/LVDS clock receiver is running,

but the derived logic clock signal is not enabled.

Standby (2)

In standby state, the derived logic clock signal is running.

All SPI registers are active, meaning that all SPI registers

can be accessed for read or write operations. All other blocks

are disabled.

Idle

In the idle state, all internal blocks are enabled, except the

sequencer block. The sensor is ready to start grabbing

images as soon as the sequencer block is enabled.

Running

In running state, the sensor is enabled and grabbing

images. The sensor can be operated in global master/slave

modes.

User Actions: Power Up Functional Mode Sequences

Power Up Sequence

Figure 17 shows the power up sequence of the sensor. The

figure indicates that the first supply to ramp−up is the

vdd_18 supply, followed by vdd_33 and vdd_pix

respectively. It is important to comply with the described

sequence. Any other supply ramping sequence may lead to

high current peaks and, as consequence, a failure of the

sensor power up.

The clock input should start running when all supplies are

stabilized. When the clock frequency is stable, the reset_n

signal can be de−asserted. After a wait period of 10 ms, the

power up sequence is finished and the first SPI upload can

be initiated.

NOTE: The ‘clock input’ can be the CMOS PLL clock

input (clk_pll), or the LVDS clock input

(lvds_clock_inn/p) in case the PLL is bypassed.

Figure 17. Power Up Sequence

reset_n

vdd_18

vdd_33

clock input

vdd_pix

> 10us> 10us> 10us > 10us

SPI Upload

> 10us

Enable Clock Management − Part 1

The ‘Enable Clock Management’ action configures the

clock management blocks and activates the clock generation

and distribution circuits in a pre−defined way. First, a set of

clock settings must be uploaded through the SPI register.

These settings are dependent on the desired operation mode

of the sensor.

Table 6 shows the SPI uploads to be executed to configure

the sensor for P1−SN/SE 8−bit and 10−bit serial, with and

without the PLL.

If the PLL is not used, the LVDS clock input must be

running.

It is important to follow the upload sequence listed in

Table 6.

Use of Phase Locked Loop

If PLL is used, the PLL is started after the upload of the

SPI registers. The PLL requires (dependent on the settings)

some time to generate a stable output clock. A lock detect

circuit detects if the clock is stable. When complete, this is

flagged in a status register.

Check the PLL_lock flag 24[0] by reading the SPI

Management− Part 2’ action can be continued. When PLL

is not used, this step can be bypassed as shown in Figure 16

on page 14.

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