1.35V DDR3L SDRAM内存详解：低电压版DDR3规格

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本文档主要介绍了MT系列的低电压DDR3L SDRAM器件，如MT41K512M4、MT41K256M8和MT41K128M16，它们是标准DDR3 SDRAM的1.35V版本，旨在降低功耗并保持与1.5V DDR3兼容。以下是一些关键知识点： 1. **电压规格**：DDR3L SDRAM支持1.35V（1.283-1.45V）的工作电压，这使得它适用于对电源效率有较高要求的应用，同时仍然兼容1.5V DDR3的标准工作范围（±0.075V）。 2. **数据传输**：采用差分双向数据 strobe，提供高效的数据传输能力。8n-bit prefetch architecture确保了数据预取性能，增强了内存访问速度。 3. **时序控制**：设备具有可编程的CAS (Column Address Strobe) 延迟（CL，读取延迟）、POSTED CAS附加延迟（AL）和写入CAS延迟（CWL），以及固定的8字节 Burst Length (BL) 和 4字节 Burst Chop (BC)，可通过模制寄存器集(MRS)进行动态调整。 4. **刷新功能**：支持自刷新模式，能够在高达95°C的温度下实现95°C下64ms和8192周期刷新，超过85°C时切换到8ms刷新周期，以适应更宽的温度范围。 5. **节能特性**：自动自刷新(ASR)功能有助于在无需连续刷新时节省能源，而Write Leveling则有助于优化写操作以减少功耗。 6. **多功能寄存器**：设备包含一个多用途寄存器，用于配置和管理不同的功能选项，增加了灵活性。 7. **输出驱动器校准**：为了优化信号质量，输出驱动器提供了校准选项，确保信号的准确性和一致性。 8. **封装标记**：文档提到的MT41K512M4型号为512MB x 4配置，其他型号也有相应的不同容量配置。 DDR3L SDRAM以其低电压设计和兼容性，为系统设计师提供了能在低功耗和性能之间找到良好平衡的选择，特别是在对功耗敏感的嵌入式系统和移动设备应用中。了解这些特性对于正确选择和使用此类内存至关重要。

Figure 4: 256 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(32,768 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

SW1 SW2

DDQ

TT(WR)

TT,nom

SW1 SW2

DDQ

TT,nom

TT(WR)

SW1 SW2

DDQ

TT,nom

TT(WR)

BC4 (burst chop)

BC4

Write

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

Address

A12

SSQ

OTF

Figure 5: 128 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

SW1

SW2

DDQ

BC4

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

DDQ

TT,nom

TT(WR)

TT,nom

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

09005aef83ed2952

2Gb_DDR3L.pdf - Rev. N 07/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef83ed2952

2Gb_DDR3L.pdf - Rev. N 07/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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