Philips I2C总线规范概述

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"Philips_I2C_spec.pdf 是一份详细阐述I2C（Inter-Integrated Circuit）总线规范的文档，版本2.1，由Philips Semiconductors发布于2000年1月。这份文档介绍了I2C总线的概念、特性、数据传输方式、仲裁机制以及支持的地址格式和扩展模式，旨在帮助设计师和制造商理解并应用I2C总线技术。 I2C总线是一种两线制的串行通信协议，由Philips（现NXP半导体）在1982年开发，旨在简化微控制器与其他设备之间的通信。该协议有以下几个主要优势： 1. 设计者受益： - 简化硬件设计：I2C只需要两根线即可实现双向通信，降低了硬件复杂性。 - 易于软件编程：相对简单的协议使得软件实现更为便捷。 2. 制造商受益： - 成本效益：减少线缆和连接器，降低了制造成本。 - 兼容性：I2C总线标准允许不同厂家的设备无缝对接。文档主要内容包括： 3. I2C总线概念： - 描述了I2C总线的基本架构和工作原理。 4. 一般特性： - 详述了总线的速度等级、电源电压、最大设备数量等特性。 5. 位传输： - 解释了数据有效性、启动（START）和停止（STOP）条件。 6. 数据传输： - 定义了字节格式和确认（Acknowledge）机制。 7. 仲裁与时钟生成： - 阐述了同步过程、总线仲裁策略以及时钟同步机制作为握手功能的用途。 8. 7位地址格式： - 介绍7位地址系统，定义了第一字节中的各个位如何分配。 9. 扩展标准模式： - 讨论了对标准模式I2C总线规范的增强和扩展。 10. 7位地址寻址： - 分析了7位地址的定义，包括通用呼叫地址、启动字节和与CBUS兼容性。 11. 快速模式（Fast Mode）： - 提供了支持更高数据速率的快速模式I2C的规格。 12. 高速模式（Hs-Mode）： - 描述了高速传输的特性，允许更快的数据传输速度。这些规范对于理解和实现I2C总线通信至关重要，无论是对于嵌入式系统设计还是电子产品的开发，都是一个重要的参考指南。"

Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

剩余45页未读，继续阅读

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