XU ET AL. VOL. 5
’
NO. 6
’
5031– 5037
’
2011
www.acsnano.org
5031
April 29, 2011
C 2011 American Chemical Society
Top-Gated Graphene Field-Effect
Transistors with High Normalized
Transconductance and Designable
Dirac Point Voltage
Huilong Xu, Zhiyong Zhang,
*
Haitao Xu, Zhenxing Wang, Sheng Wang, and Lian-Mao Peng
*
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, China
G
raphene is considered as a promis-
ing material for high-performance
nanoelectronics due to its extremely
high carrier mobility, the ultimate thin body,
and stability.
15
Because of the lack of an
intrinsic band gap,
2,3
graphene is believed
to be more suitable for radio frequency
(RF) analog electronics,
4,5
instead of digital
applications where a large current on/off
ratio is required. Recently, graphene fi eld-
effect transistors (G-FETs) with a cutoff fre-
quency (f
T
) of up to 100300 GHz were
successively fabricated,
6,7
and their advan-
tages for RF applications were amply de-
monstrated. Besides f
T
, there are some other
device parameters that are also important
and need to be optimized. These para-
meters include transconductance and the
working point of the device, that is, the
Dirac point voltage. The transconductance
of a transistor represents the amplifying
ability which is very important for, among
others, signal and power amplifier and fre-
quency doubler applications,
810
and the
Dirac point voltage will affect the dc supply
voltage needed in real applications.
810
It is
well-known that the quality of the gate
oxide is one of the key factors determining
the transconductance of a real device, and a
high-quality dielectric layer is therefore highly
desirable on pristine graphene which
couldleadtobothhighcarriermobility
(less scatters) and large gate capacitance.
Several dielectrics have been successfully
grown on graphene via, for example, de-
positing functionalization and buffering
layers to reduce scattering and retain high
mobility, but the additional buffering layers
significantly increase the effective thickness
of the gate dielectric layer and reduce the
gate oxide capacitance.
1118
Very recently,
an ultrathin yttrium oxide layer was grown
on graphene with an equivalent oxide thick-
ness (EOT) of about 1.5 nm and an extre-
mely large oxide capacitance of more than
2.2 μF/cm
2
.
1921
However, mobilities for
both electron and hole were found to be
lower than 2000 cm
2
/V
3
s.
1921
It is t he
aim of this paper t o report a simple an-
nealing procedure that simultaneously
yields a high carrier mobility of mor e than
5000 cm
2
/V
3
s and large gate capacitance
of about 1.5 μF/cm
2
.
Although it is well-known that the posi-
tion of the Dirac point is affected by work
function of the contact metal in back-gated
graphene FETs,
22
few works focused on
controlling the Dirac point of top-gated
graphene FETs, which is another significant
parameter for FET, similar to threshold vol-
tage in conventional FETs. Similar to carbon
nanotube FETs,
23
effective and stable dop-
ing is not easy in graphene, and the Dirac
voltage of graphene FETs cannot thus be
readily adjusted by tuning the dopant den-
sity of the graphene channel as in silicon
* Address correspondence to
zyzhang@pku.edu.cn,
lmpeng@pku.edu.cn.
Received for review March 24, 2011
and accepted April 29, 2011.
Published online
10.1021/nn201115p
ABSTRACT High-performance graphene field-effect transistors (G-FETs) are fabricated with
carrier mobility of up to 5400 cm
2
/V
3
s and top-gate efficiency of up to 120 (relative to that of back
gate with 285 nm SiO
2
) simultaneously through growing high-quality Y
2
O
3
gate oxide at high
oxidizing temperature. The transconductance normalized by dimension and drain voltage is found to
reach 7900 μF/V
3
s, which is among the largest of the published graphene FETs. In an as-fabricated
graphene FET with a gate length of 310 nm, a peak transconductance of 0.69 mS/μm is realized, but
further improvement is seriously hindered by large series resistance. Benefiting from highly efficient
gate control over the graphene channel, the Dirac point voltage of the graphene FETs is shown to be
designable via simply selecting a gate metal with an appropriate work function. It is demonstrated
that the Dirac point voltage of the graphene FETs can be adjusted from negative to positive,
respectively, via changing the gate material from Ti to Pd.
KEYWORDS: graphene
.
field-effect transistor
.
transconductance
.
Dirac point
voltage
ARTICLE