PowerPC e300内核使用手册：开发者入门必备

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"e300coreRM 是一份关于powerpc e300内核的使用说明手册，适用于e300系列的多个型号，包括e300c1、e300c2、e300c3和e300c4。这份文档由Freescale Semiconductor（现为NXP Semiconductors的一部分）出版，日期为2007年12月，是开发者，尤其是新手入门的重要参考资料。" 本文档详细介绍了e300 PowerArchitecture™ Core家族的特性与功能，旨在帮助开发人员理解和利用这些处理器核心进行系统和软件设计。e300系列是针对嵌入式应用设计的低功耗、高性能的处理器，广泛应用于汽车电子、工业控制、通信设备等领域。在"e300CoreRM"中，读者可以期待获取以下关键知识点： 1. e300系列核心架构：手册将详细介绍e300系列的核心架构，包括其指令集、寄存器配置、内存管理单元（MMU）、中断处理机制等。 2. 处理器时钟和电源管理：讲解如何配置和管理处理器的时钟频率，以及如何实现低功耗操作，这对于电池供电的设备尤为重要。 3. 中断和异常处理：描述了e300内核如何处理中断和异常，以及如何设置中断向量表和中断处理程序。 4. 硬件调试接口：可能涵盖IEEE 1149.1 JTAG调试标准，允许通过硬件接口进行调试和测试。 5. 存储系统：包括内部缓存、外部存储器接口（如DDR、SRAM等）的配置和优化。 6. 外设接口：可能涉及e300系列支持的各种外设接口，如UART、SPI、I2C等，并提供如何与这些接口交互的指导。 7. 编程模型：介绍如何编写兼容e300内核的软件，包括指针对齐、数据类型和异常处理等方面的注意事项。 8. 性能优化技巧：提供代码优化建议，帮助开发人员最大化利用处理器性能。 9. 系统初始化：描述从复位到运行用户代码的系统启动过程，包括初始化内存、设置时钟和配置外设。 10. 安全性和可靠性：可能包含关于保护机制、错误检测和纠正策略的信息，以确保系统的稳定运行。请注意，虽然文档本身不授予版权许可来设计或制造基于其中信息的集成电路，但它是理解Freescale Semiconductor e300内核的关键资源，对于任何使用这些处理器的开发工作都是必不可少的参考材料。

e300 Power Architecture Core Family Reference Manual, Rev. 4

xvi Freescale Semiconductor

Figures

Figure

Number Title

Page

Number

5-1 Machine Status Save/Restore Register 0 (SRR0) ................................................................... 5-8

5-2 Machine Status Save/Restore Register 1 (SRR1) ................................................................... 5-8

5-3 Critical Interrupt Save/Restore Register 0 (CSRR0) ............................................................ 5-10

5-4 Critical Interrupt Save/Restore Register 1 (CSRR1) ............................................................ 5-11

5-5 SPRGn Register .................................................................................................................... 5-11

5-6 Machine State Register (MSR) ............................................................................................. 5-12

6-1 MMU Conceptual Block Diagram—32-Bit Implementations................................................ 6-5

6-2 e300 Core IMMU Block Diagram .......................................................................................... 6-6

6-3 e300 Core DMMU Block Diagram......................................................................................... 6-7

6-4 Address Translation Types...................................................................................................... 6-9

6-5 General Flow of Address Translation (Real Addressing Mode and Block) ......................... 6-11

6-6 General Flow of Page and Direct-Store Interface Address Translation................................ 6-13

6-7 Segment Register and TLB Organization ............................................................................. 6-24

6-8 Page Address Translation Flow for 32-Bit Implementations—TLB Hit.............................. 6-26

6-9 Primary Page Table Search—Conceptual Flow.................................................................... 6-28

6-10 Secondary Page Table Search Flow—Conceptual Flow.......................................................6-29

6-11 DMISS and IMISS Registers ................................................................................................ 6-32

6-12 DCMP and ICMP Registers.................................................................................................. 6-32

6-13 HASH1 and HASH2 Registers ............................................................................................. 6-33

6-14 Required Physical Address Register (RPA).......................................................................... 6-33

6-15 Flow for Example Software Table Search Operation ........................................................... 6-35

6-16 Check and Set R and C Bit Flow .......................................................................................... 6-36

6-17 Page Fault Setup Flow .......................................................................................................... 6-37

6-18 Setup for Protection Violation Exceptions............................................................................ 6-38

7-1 Pipelined Execution Unit ........................................................................................................ 7-3

7-2 Instruction Flow Diagram for the e300c1............................................................................... 7-4

7-3 Instruction Flow Diagram for the e300c2............................................................................... 7-5

7-4 Instruction Flow Diagram for the e300c3 and e300c4............................................................ 7-6

7-5 e300 Core Processor Pipeline Stages...................................................................................... 7-8

7-6 Instruction Timing—Cache Hit............................................................................................. 7-12

7-7 Instruction Timing—Cache Miss.......................................................................................... 7-15

7-8 Branch Instruction Timing ....................................................................................................7-21

7-9 Instruction Timing—Integer Execution in the e300c1Core.................................................. 7-22

7-10 Instruction Timing—Integer Execution in the e300c2 and e300c3 ...................................... 7-23

8-1 Core Interface Signals............................................................................................................. 8-2

11-1 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 11-3

11-2 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 11-4

11-3 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................. 11-6

e300 Power Architecture Core Family Reference Manual, Rev. 4

Freescale Semiconductor xvii

Tables

Table

Number Title

Page

Number

Ta bl e s

1-1 e300 HID0 Bit Descriptions.................................................................................................. 1-23

1-2 Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out ...........................................1-26

1-3 HID1 Bit Descriptions .......................................................................................................... 1-26

1-4 e300HID2 Bit Descriptions................................................................................................... 1-26

1-5 Interrupt Classifications ...................................................................................................... 1-34

1-6 Exceptions and Interrupts...................................................................................................... 1-35

1-7 Differences Between e300 and G2_LE Cores ...................................................................... 1-42

1-8 Differences Between e300 Cores.......................................................................................... 1-43

2-1 FPSCR Bit Settings................................................................................................................. 2-3

2-2 Architectural PVR Field Descriptions .................................................................................... 2-6

2-3 Assigned PVR Values ............................................................................................................. 2-6

2-4 MSR Bit Settings .................................................................................................................... 2-7

2-5 e300 HID0 Field Descriptions .............................................................................................. 2-12

2-6 HID0[SBCLK] and HID0[ECLK] clk_out Configuration.................................................... 2-15

2-7 HID1 Bit Settings..................................................................................................................2-15

2-8 e300 HID2 Field Descriptions .............................................................................................. 2-16

2-9 DCMP and ICMP Bit Settings.............................................................................................. 2-19

2-10 HASH1 and HASH2 Bit Settings ......................................................................................... 2-20

2-11 RPA Bit Settings ................................................................................................................... 2-20

2-12 System Version Register (SVR) Bit Settings ........................................................................ 2-24

2-13 Instruction Address Breakpoint Register (IABR and IABR2) Bit Settings.......................... 2-25

2-14 Instruction Address Breakpoint Control Registers (IBCR) .................................................. 2-25

2-15 Data Address Breakpoint Registers (DABR and DABR2) Bit Settings............................... 2-26

2-16 Data Address Breakpoint Control Registers (DBCR)........................................................... 2-27

3-1 Endian Mode Indication.......................................................................................................... 3-2

3-2 Memory Operands................................................................................................................... 3-2

3-3 Integer Arithmetic Instructions ............................................................................................. 3-10

3-4 Integer Compare Instructions................................................................................................ 3-11

3-5 Integer Logical Instructions .................................................................................................. 3-12

3-6 Integer Rotate Instructions.................................................................................................... 3-13

3-7 Integer Shift Instructions....................................................................................................... 3-13

3-8 Floating-Point Arithmetic Instructions ................................................................................. 3-14

3-9 Floating-Point Multiply-Add Instructions ............................................................................ 3-14

3-10 Floating-Point Rounding and Conversion Instructions......................................................... 3-15

3-11 Floating-Point Compare Instructions.................................................................................... 3-15

3-13 Floating-Point Move Instructions ......................................................................................... 3-16

3-14 Integer Load Instructions ...................................................................................................... 3-17

3-15 Integer Store Instructions...................................................................................................... 3-18

3-16 Integer Load and Store with Byte-Reverse Instructions .......................................................3-19

3-17 Integer Load and Store Multiple Instructions ....................................................................... 3-20

3-18 Integer Load and Store String Instructions ........................................................................... 3-20

e300 Power Architecture Core Family Reference Manual, Rev. 4

xviii Freescale Semiconductor

Tables

Table

Number Title

Page

Number

3-19 Floating-Point Load Instructions .......................................................................................... 3-21

3-20 Floating-Point Store Instructions .......................................................................................... 3-22

3-21 Branch Instructions ............................................................................................................... 3-23

3-22 Condition Register Logical Instructions ............................................................................... 3-24

3-23 Trap Instructions ................................................................................................................... 3-24

3-24 Move fo/from Condition Register Instructions..................................................................... 3-24

3-25 Memory Synchronization Instructions—UISA .................................................................... 3-26

3-26 Move from Time Base Instruction ........................................................................................ 3-26

3-27 Memory Synchronization Instructions—VEA...................................................................... 3-27

3-28 User-Level Cache Instructions.............................................................................................. 3-27

3-29 System Linkage Instructions.................................................................................................3-28

3-30 Move to/from Machine State Register Instructions .............................................................. 3-29

3-31 Move to/from Special-Purpose Register Instructions...........................................................3-29

3-32 Implementation-Specific SPR Encodings (mfspr)............................................................... 3-29

3-33 Performance Monitor APU Instructions ............................................................................... 3-32

3-34 Segment Register Manipulation Instructions........................................................................ 3-32

3-35 Translation Lookaside Buffer Management Instructions...................................................... 3-33

4-1 Combinations of W, I, and M Bits .......................................................................................... 4-8

4-2 MEI/MESI State Definitions...................................................................................................4-9

4-3 Memory Coherency Actions on Load Operations ................................................................ 4-12

4-4 Memory Coherency Actions on Store Operations ................................................................ 4-12

4-5 e300c1 PLRU Replacement Way Selection.......................................................................... 4-23

4-6 e300c2 PLRU Replacement Way Selection.......................................................................... 4-23

4-7 PLRU Bit Update Rules........................................................................................................4-25

4-8 e300 Bus Operations Caused by Cache Control Instructions ............................................... 4-29

4-9 Snoop Response to CSB Transactions.................................................................................. 4-30

4-10 Cache Organization............................................................................................................... 4-33

4-11 HID0 Bits Used to Perform Cache Locking ......................................................................... 4-33

4-12 HID2 Bits Used to Perform Cache Way-locking .................................................................. 4-34

4-13 MSR Bits Used to Perform Cache Locking.......................................................................... 4-34

4-14 Example BAT Settings for Cache Locking ........................................................................... 4-35

4-15 MSR Bits for Disabling Interrupts ........................................................................................ 4-36

4-16 e300c1 and e300c4 Core DWLCK[0–2] Encodings............................................................. 4-38

4-17 e300c2 and e300c3 Core DWLCK[0–2] Encodings............................................................. 4-39

4-18 Example BAT Settings for Cache Locking ........................................................................... 4-40

4-19 MSR Bits for Disabling Interrupts ........................................................................................ 4-41

4-20 e300c1 and e300c4 Core IWLCK[0–2] Encodings .............................................................. 4-43

4-21 e300c2 Core IWLCK[0–2] Encodings.................................................................................. 4-44

5-1 Interrupt Classifications .......................................................................................................... 5-3

5-2 Interrupts and Exception Conditions....................................................................................... 5-3

5-3 Interrupt Priorities................................................................................................................... 5-6

e300 Power Architecture Core Family Reference Manual, Rev. 4

Freescale Semiconductor xix

Tables

Table

Number Title

Page

Number

5-4 SRR1 Bit Settings for Machine Check Interrupts................................................................... 5-9

5-5 SRR1 Bit Settings for Program Interrupts .............................................................................. 5-9

5-6 SRR1 Bit Settings for Software Table Search Operations.................................................... 5-10

5-7 Conventional Uses of SPRG0–SPRG7................................................................................. 5-11

5-8 MSR Bit Settings .................................................................................................................. 5-12

5-9 IEEE Floating-Point Exception Mode Bits........................................................................... 5-14

5-10 MSR Setting Due to Interrupt ............................................................................................... 5-17

5-11 Hard Reset MSR Value and Interrupt Vector........................................................................ 5-18

5-12 Settings Caused by Hard Reset ............................................................................................. 5-19

5-13 Soft Reset Interrupt—Register Settings................................................................................ 5-20

5-14 Machine Check Interrupt—Register Settings ....................................................................... 5-22

5-15 DSI Interrupt—Register Settings.......................................................................................... 5-23

5-16 External Interrupt—Register Settings................................................................................... 5-25

5-17 Alignment Interrupt—Register Settings ............................................................................... 5-26

5-18 Access Types......................................................................................................................... 5-27

5-19 Critical Interrupt—Register Settings .................................................................................... 5-31

5-20 Trace Interrupt—Register Settings ....................................................................................... 5-32

5-21 Instruction and Data TLB Miss Interrupts—Register Settings.............................................5-34

5-22 Instruction Address Breakpoint Interrupt—Register Settings .............................................. 5-35

5-23 Breakpoint Action for Multiple Modes Enabled for the Same Address............................... 5-35

5-24 System Management Interrupt—Register Settings............................................................... 5-36

6-1 MMU Features Summary........................................................................................................ 6-2

6-2 Access Protection Options for Pages ...................................................................................... 6-9

6-3 Translation Exception Conditions......................................................................................... 6-14

6-4 Other MMU Exception Conditions....................................................................................... 6-15

6-5 Instruction Summary—MMU Control.................................................................................. 6-17

6-6 MMU Registers..................................................................................................................... 6-17

6-7 Table Search Operations to Update History Bits—TLB Hit Case........................................ 6-20

6-8 Model for Guaranteed R and C Bit Settings ......................................................................... 6-22

6-9 Implementation-Specific Resources for Table Search Operations........................................ 6-30

6-10 Implementation-Specific SRR1 Bits..................................................................................... 6-31

6-11 DCMP and ICMP Bit Settings.............................................................................................. 6-32

6-12 HASH1 and HASH2 Bit Settings ......................................................................................... 6-33

6-13 RPA Bit Settings ................................................................................................................... 6-33

7-1 Branch Instructions ............................................................................................................... 7-28

7-2 System Register Instructions.................................................................................................7-28

7-3 Condition Register Logical Instructions ............................................................................... 7-29

7-4 Integer Instructions ............................................................................................................... 7-29

7-5 Floating-Point Instructions.................................................................................................... 7-31

7-6 Load and Store Instructions ..................................................................................................7-33

8-1 Summary of Selected Internal Signals.................................................................................... 8-2

e300 Power Architecture Core Family Reference Manual, Rev. 4

xx Freescale Semiconductor

Tables

Table

Number Title

Page

Number

8-2 Core PLL Configuration ......................................................................................................... 8-4

9-1 e300 Core Programmable Power Modes ................................................................................ 9-2

10-1 Other Debug and Support Register Bits................................................................................ 10-3

10-2 Debug Interrupts and Conditions.......................................................................................... 10-3

10-3 Single-Address Matching Bit Settings.................................................................................. 10-5

10-4 Two-Address OR Matching .................................................................................................. 10-5

10-5 Address Matching for Inside Address Range ....................................................................... 10-6

10-6 Address Matching for Outside Address Range..................................................................... 10-6

11-1 Performance Monitor Registers–Supervisor Level............................................................... 11-2

11-2 Performance Monitor Registers–User Level (Read-Only) ................................................... 11-2

11-3 PMGC0 Field Descriptions................................................................................................... 11-3

11-4 PMLCa0–PMLCa3 Field Descriptions................................................................................. 11-5

11-5 PMC0–PMC3 Field Descriptions ......................................................................................... 11-6

11-6 Performance Monitor APU Instructions ............................................................................... 11-7

11-7 Processor States and PMLCa0–PMLCa3 Bit Settings........................................................ 11-10

11-8 Event Types..........................................................................................................................11-11

11-9 Performance Monitor Event Selection................................................................................ 11-12

A-1 Complete Instruction List Sorted by Mnemonic.................................................................... A-1

A-2 Complete Instruction List Sorted by Opcode......................................................................... A-8

A-3 Integer Arithmetic Instructions ............................................................................................ A-15

A-4 Integer Compare Instructions............................................................................................... A-16

A-5 Integer Logical Instructions .................................................................................................A-16

A-6 Integer Rotate Instructions................................................................................................... A-16

A-7 Integer Shift Instructions...................................................................................................... A-17

A-8 Floating-Point Arithmetic Instructions ................................................................................ A-17

A-9 Floating-Point Multiply-Add Instructions ........................................................................... A-18

A-10 Floating-Point Rounding and Conversion Instructions........................................................ A-18

A-11 Floating-Point Compare Instructions................................................................................... A-18

A-12 Floating-Point Status and Control Register Instructions......................................................A-18

A-13 Integer Load Instructions ..................................................................................................... A-19

A-14 Integer Store Instructions..................................................................................................... A-19

A-15 Integer Load and Store with Byte-Reverse Instructions ...................................................... A-20

A-16 Integer Load and Store Multiple Instructions ...................................................................... A-20

A-17 Integer Load and Store String Instructions .......................................................................... A-20

A-18 Memory Synchronization Instructions................................................................................. A-21

A-19 Floating-Point Load Instructions ......................................................................................... A-21

A-20 Floating-Point Store Instructions ......................................................................................... A-21

A-21 Floating-Point Move Instructions ........................................................................................ A-22

A-22 Branch Instructions .............................................................................................................. A-22

A-23 Condition Register Logical Instructions .............................................................................. A-22

A-24 System Linkage Instructions................................................................................................ A-22

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