TMS320F28xx硬件设计全方位指南：避免昂贵错误与高效调试

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《DSPTMS320F28xx硬件设计指南》是一份针对TI公司TMS320F28xx系列数字信号控制器（DSC）的系统级硬件设计参考资料，由Pradeep Shinde编撰，于2008年发布。该指南主要针对该系列产品的复杂外围设备，如运行在较高时钟频率上的定时器、计数器等，以及它们与低级别的模拟信号接口，例如通过板上模拟-数字转换器（ADC）。指南的目标是为系统级硬件设计、元器件选择、电路图设计到PCB布局提供实用的指导，以减少项目开发过程中由于硬件错误导致的高额成本和时间浪费。在系统调试阶段，特别是原型板验证时，这份报告强调了以下几个关键知识点： 1. **时钟生成**：对于多任务并行操作，精确和稳定的时钟管理至关重要，包括主时钟的配置、分频和同步，以及确保各个模块之间的时钟同步。 2. **JTAG接口**：JTAG接口用于调试和编程，指南提供了使用JTAG进行芯片配置、编程和故障检测的最佳实践。 3. **电源管理**：涵盖电源分配、滤波、保护电路的设计，确保稳定的工作电压和有效的电源噪声抑制。 4. **模拟输入至ADC接口**：详细解释了如何高效地连接和处理来自传感器或信号源的模拟信号，以提高数据采集的准确性和可靠性。 5. **GPIO连接**：通用输入/输出（GPIO）在许多应用中扮演着重要角色，指南讨论了如何合理规划GPIO引脚的分配，以及它们在不同功能中的使用。 6. **测试与调试**：指南提供了有效的测试策略和工具，帮助开发者尽早发现和修复硬件问题，降低调试成本。 7. **电磁兼容性（EMI）与电磁兼容性（EMC）**：介绍了如何在设计中考虑和满足EMI和EMC标准，以防止干扰和保护系统免受外部电磁环境的影响。 8. **信号路由和布局**：每个部分都包含信号完整性（SI）、阻抗控制和布局技巧，确保信号在电路板上的传输质量和性能。通过阅读这份应用报告，设计师能够获得一个全面的框架，以便在TMS320F28xx硬件设计中避免常见问题，提高项目的成功率和效率。

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ExternalClockSignal

(Toggling0-V )

DDIO

XCLKIN X1 X2

a)Usinga3.3VExternalOscillator

ExternalClockSignal

(Toggling0-V )

XCLKIN X1

b)Usinga1.8V/1.9VExternalOscillator

3.1.2 Loss of Input Clock - Limp Mode

3.1.3 XCLKOUT

Handling of Different Hardware Building Blocks

Connect the output of the external oscillator to the F280x and F28xxx parts as shown in Figure 4 , based

upon the level. It is important to connect X1 or XCLKIN to ground as shown. If they are left open, the

frequency of CLKOUT will be incorrect and the DSC may not work properly.

Figure 4. Connecting External Oscillator to F280x/F28xxx

The F281x devices select the external clock oscillator part that toggles between 0 - V

(0 – 1.8 V/1.9V).

Note: If you are using a 3.3 V external oscillator for an F281x system, use a 3.3 V to 1.8 V/1.9 V

voltage translator device equivalent to TI’s SN74LVC1G14 - SN74LVC1G14 Single

Schmitt-Trigger Inverter Data Sheet (SCES218 ) .

The PLL still issues a limp-mode clock if the input clock, OSCCLK, is removed or absent. The limp-mode

clock continues to clock the CPU and peripherals at a typical frequency of 1 MHz - 5 MHz. Limp mode is

not specified to work from power-up, but only after input clocks have been present. In PLL bypass mode,

the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or

absent. The watchdog counter stops decrementing with the failure of the input clock and does not change

with the limp-mode clock. These conditions could be used by the application firmware to detect the input

clock failure and initiate a necessary shut-down procedure for the system.

Note: Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the DSC is held in reset should the input clocks ever fail.

For example, an R-C circuit can be used to trigger the XRS pin of the DSC, should the

capacitor ever get fully charged. An I/O pin can be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the Flash memory and the V

DD3VFL

rail.

The output clock signal, derived from SYSCLKOUT, is available on XCLKOUT as a general-purpose clock

source, which can be used for external wait-state generation. It also serves as a Test Point to check the

CPU clock frequency and to ensure that the PLL is working properly. At reset, XCLKOUT =

SYSCLKOUT/4; but it can be set the same as or 1/2 of SYSCLKOUT.

The XCLKOUT signal is active when reset is active. Since XCLKOUT should reflect SYSCLKOUT/4 when

reset is low, you can monitor this signal to detect if the device is being properly clocked during debug.

There is no internal pullup or pulldown on the XCLKOUT pin. The drive strength of this pin is 8 mA. If

XCLKOUT is not being used, it can be turned off by setting the CLKOFF bit to 1 in the XINTF

Configuration Register (XINTCNF2). This is an output pin of the CMOS device and should not be

terminated to ground even if it is not used.

Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs6 SPRAAS1 – March 2008

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