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首页ARM指令集详解：C语言与汇编应用指南

ARM指令集详解：C语言与汇编应用指南

ARM

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ARM指令集是针对ARM架构的编程指南，主要面向刚涉足ARM开发的嵌入式工程师。ARM指令集由阿尔特拉斯半导体有限公司（ARM Limited）提供版权，自1996年至2000年。该章节详细描述了每个ARM指令的语法、用法、适用的ARM架构版本、可能引发的异常情况以及示例代码，以便于理解其工作原理。在4.1节的"字母表顺序的ARM指令列表"部分，所有ARM指令都被罗列出来。每条指令的描述包括指令编码，即它在二进制中的表示形式；指令语法，如何在程序中正确构造；对应的ARM架构版本，确保代码的兼容性；可能出现的异常处理，提醒开发者注意潜在问题；以及伪代码示例，展示了指令在实际应用中的操作流程。此外，还有通用注意事项，解释了在指令页面上使用的各类信息类型和缩写，如`immed_n`代表n位立即数，`offset_n`指n位偏移量，这些帮助开发者理解和编写更高效、精确的代码。通过这份文档，嵌入式工程师可以系统地学习和掌握ARM指令集，从而在实际项目中编写出高效且稳定的ARM程序，实现嵌入式设备的功能和性能优化。同时，了解ARM指令集的演变和适用的架构版本变化，有助于保持代码的长期兼容性和适应性。对于初学者来说，这是一份非常重要的参考资料，可以帮助他们快速熟悉并深入理解ARM平台的编程特性。

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ARM Instructions

A4-16

ARM DDI 0100E

4.1.8 BLX (1)

This form of the BLX (Branch with Link and Exchange) instruction is used to call a Thumb subroutine from

the ARM instruction set at an address specified in the instruction. This instruction is unconditional (always

causing a change in program flow) and preserves the address of the instruction following the branch in the

link register (R14). Execution of Thumb instructions begins at the target address.

Syntax

BLX <target_addr>

where:

<target_addr> Specifies the address of the Thumb instruction to branch to. The branch target

address is calculated by:

1. Sign-extending the 24-bit signed (two’s complement) immediate to 32 bits

2. Shifting the result left two bits

3. Setting bit[1] of the result of step 2 to the H bit

4. Adding the result of step 3 to the contents of the PC, which contains the

address of the branch instruction plus 8.

The instruction can therefore specify a branch of approximately ±32MB.

Architecture version

Version 5 and above

Exceptions

None

Operation

LR = address of the instruction after the BLX instruction

T Flag = 1

PC = PC + (SignExtend(signed_immed_24) << 2) + (H << 1)

31 30 29 28 27 26 25 24 23 0

1111101H signed_immed_24

ARM Instructions

ARM DDI 0100E

A4-17

Usage

To return from a Thumb subroutine called via BLX to the ARM caller, use the Thumb instruction:

BX R14

as described in BX on page A7-32, or use this instruction on subroutine entry:

PUSH {<registers>,R14}

and this instruction to return:

POP {<registers>,PC}

To calculate the correct value of signed_immed_24, the assembler (or other toolkit component) needs to:

1. Form the base address for this branch instruction. This is the address of the instruction, plus 8. In

other words, this base address is equal to the PC value used by the instruction.

2. Subtract the base address from the target address to form a byte offset. This offset is always even,

because all ARM instructions are word-aligned and all Thumb instructions are halfword-aligned.

3. If the byte offset is outside the range −33554432 to +33554430, use an alternative code-generation

strategy or produce an error as appropriate.

4. Otherwise, set the signed_immed_24 field of the instruction to bits{25:2] of the byte offset, and the

H bit of the instruction to bit[1] of the byte offset.

Notes

Condition Unlike most other ARM instructions, this instruction cannot be executed conditionally.

Bit[24] This bit is used as bit[1] of the target address.

ARM Instructions

A4-18

ARM DDI 0100E

4.1.9 BLX (2)

This form of BLX is used to call an ARM or Thumb subroutine from the ARM instruction set, at an address

specified in a register. The branch target address is the value of register Rm, with its bit[0] forced to zero.

The instruction set to be used at the branch target is chosen by setting the CPSR T bit to bit[0] of Rm.

on the stack and re-load the stored value into the PC.

Syntax

BLX{<cond>} <Rm>

where:

<cond> Is the condition under which the instruction is executed. The conditions are defined in The

condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Rm> Is the register containing the address of the target instruction. Bit[0] of Rm is 0 to select a

target ARM instruction, or 1 to select a target Thumb instruction. If R15 is specified for

<Rm>, the results are

UNPREDICTABLE.

Architecture version

Version 5 and above

Exceptions

None

Operation

if ConditionPassed(cond) then

LR = address of instruction after the BLX instruction

T Flag = Rm[0]

PC = Rm AND 0xFFFFFFFE

Notes

ARM/Thumb state transfers

If Rm[1:0] == 0b10, the result is

UNPREDICTABLE, as branches to non word-aligned

addresses are impossible in ARM state.

31302928272625242322212019 1615 1211 876543 0

cond 00010010 SBO SBO SBO 0011 Rm

ARM Instructions

ARM DDI 0100E

A4-19

4.1.10 BX

The BX (Branch and Exchange) instruction branches to an address held in a register Rm, with an optional

switch to Thumb execution. The branch target address is the value of register Rm, with its bit[0] forced to

zero. The instruction set to be used at the branch target is chosen by setting the CPSR T bit to bit[0] of Rm.

Syntax

BX{<cond>} <Rm>

where:

<cond> Is the condition under which the instruction is executed. The conditions are defined in The

condition field on page A3-5. If <cond> is omitted, the AL (always) condition is used.

<Rm> Holds the value of the branch target address. Bit[0] of Rm is 0 to select a target ARM

instruction, or 1 to select a target Thumb instruction.

Architecture version

Version 5 and above, plus T variants of version 4

Exceptions

None

Operation

if ConditionPassed(cond) then

T Flag = Rm[0]

PC = Rm AND 0xFFFFFFFE

Notes

ARM/Thumb state transfers

If Rm[1:0] == 0b10, the result is

UNPREDICTABLE, as branches to non word-aligned

addresses are impossible in ARM state.

Use of R15 Register 15 can be specified for <Rm>, but doing so is discouraged.

In a BX R15 instruction, R15 is read as normal for ARM code, that is, it is the address of

the BX instruction itself plus 8. The result is to branch to the second following word,

executing in ARM state. This is precisely the same effect that would have been obtained if

a B instruction with an offset field of 0 had been executed, or an ADD PC,PC,#0 or MOV

PC,PC instruction. In new code, use these instructions in preference to the more complex

BX PC instruction.

31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 0

cond 00010010 SBO SBO SBO 0001 Rm

ARM Instructions

A4-20

ARM DDI 0100E

4.1.11 CDP

The CDP (Coprocessor Data Processing) instruction tells the coprocessor whose number is cp_num to

perform an operation that is independent of ARM registers and memory. If no coprocessors indicate that

they can execute the instruction, an Undefined Instruction exception is generated.

Syntax

CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>

CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>

where:

<cond> Is the condition under which the instruction is executed. The conditions are defined

in The condition field on page A3-5. If <cond> is omitted, the AL (always)

condition is used.

CDP2 Causes the condition field of the instruction to be set to 0b1111. This provides

additional opcode space for coprocessor designers. The resulting instructions can

only be executed unconditionally.

<coproc> Specifies the name of the coprocessor, and causes the corresponding coprocessor

number to be placed in the cp_num field of the instruction. The standard generic

coprocessor names are p0, p1, ..., p15.

<opcode_1> Specifies (in a coprocessor-specific manner) which coprocessor operation is to be

performed.

<CRd> Specifies the destination coprocessor register for the instruction.

<CRn> Specifies the coprocessor register that contains the first operand for the instruction.

<CRm> Specifies the coprocessor register that contains the second operand for the

instruction.

<opcode_2> Specifies (in a coprocessor-specific manner) which coprocessor operation is to be

performed.

Architecture version

CDP is in Version 2 and above.

CDP2 is in Version 5 and above.

Exceptions

Undefined Instruction

31 28 27 26 25 24 23 20 19 16 15 12 11 8 7 5 4 3 0

cond 1110 opcode_1 CRn CRd cp_num opcode_20 CRm

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