![](https://csdnimg.cn/release/download_crawler_static/85398076/bg6.jpg)
.
4: begin if(BGA1>651)begin FT8=1'b1; BGA1<=0; end //
接收波特=19200*16
else begin FT8=1'b0; BGA1 <= BGA1+ 4;end
if(BGA>15625)begin FT=1'b1; FT8=1'b1;
BGA1<=0;BGA<=0; end // 发送波特=19200
else begin FT=1'b0; BGA <= BGA+ 6;end
end
5: begin if(BGA1>244)begin FT8=1'b1; BGA1<=0; end
// 接收波特=38400*16
else begin FT8=1'b0; BGA1 <= BGA1+ 3;end
if(BGA>15625)begin FT=1'b1;FT8=1'b1;
BGA1<=0; BGA<=0; end // 发送波特=38400
else begin FT=1'b0; BGA <= BGA+ 12;end
end
6: begin if(BGA1>217)begin FT8=1'b1; BGA1<=0; end
// 接收波特=115200*16
else begin FT8=1'b0; BGA1 <= BGA1+ 8;end
if(BGA>434) begin FT=1'b1;FT8=1'b1;
BGA1<=0; BGA<=0; end // 发送波特=115200
else begin FT=1'b0; BGA <= BGA+ 1;end
end
7: begin if(BGA1>122)begin FT8=1'b1; BGA1<=0; end
// 接收波特=128000*16
else begin FT8=1'b0; BGA1 <= BGA1+ 5;end
if(BGA>3125) begin FT=1'b1;
BGA<=0;FT8=1'b1; BGA1<=0; end // 发送波特=128000
else begin FT=1'b0; BGA <= BGA+ 8;end
end
default:begin BGA<=0;FT=1'b0;end
endcase
endmodule
//接收模块
module
trans_r(clk_r,rst_r,BTI_r,RxD_r,RxD_data_r,wren_r,addro_r,RxD_end);
input clk_r,rst_r,RxD_r,BTI_r;
output [7:0]RxD_data_r;
. . .