ANSI/ESDA/JEDEC JS-001-2023
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• the current from the supply pin group (for example, VDDIO) is required for the function of an
electrical circuit (I/O driver) that connects (high/low impedance) to that non-supply pin; or
• a parasitic path exists between a non-supply and supply pin group (for example, open-drain
type non-supply pin to a VCC supply pin group that connects to a nearby N-well guard ring).
cloned non-supply (IO) pin. Any of a set of input, output, or bidirectional pins using the same IO
cell and electrical schematic and sharing the same associated supply pin group(s), including ESD
power clamp(s).
coupled non-supply pin pair. Two pins, such as differential amplifier inputs or low-voltage
differential signaling (LVDS) pins, having an intended direct current path in between, such as a
pass gate or resistor.
NOTE: These pairs include analog and digital differential pairs and other special function pairs (for example,
D+/D-, XTALin/XTALout, RFin/RFout, TxP/TxN, RxP/RxN, CCP_DP/CCN_DN, etc.).
ESD withstand voltage; withstand threshold. The highest voltage level not causing device
failure with the device passing all tests performed at lower voltage levels.
NOTE: See note under “failure window” definition.
exposed pad. An exposed metal plate on an IC package.
NOTE: This metal plate may or may not be electrically connected to the die.
NOTE: If the exposed pad supports the die, it might be called a die attach pad or thermal pad (see
ESDA/JEDEC JTR001 for further information).
failure window. An intermediate range of stress conditions inducing failure in a particular device
type while the device type can pass some higher and lower stress conditions than this range.
NOTE: For example, a device with a failure window may pass a 500-volt test, fail a 1000-volt test, and pass
a 2000-volt test. Hence, the failure window of the device is between 500 volts and 2000 volts. The withstand
voltage of this device is 500 volts, as this is the highest passing level before the 1kV failure.
feedthrough. A direct or indirect (via a series resistor) connection from a pad cell layout allowing
additional elements not included in the pad cell to make electrical connections to the bond pad (see
Annex A).
HBM ESD tester; HBM simulator. Equipment that applies a simulated human body model (HBM)
ESD stress to a device.
human body model (HBM) ESD. An electrostatic discharge (ESD) event meeting the waveform
criteria specified in this standard approximating the discharge from the fingertip of a typical human
being to a grounded device.
Ips (peak current value). The current value determined by linear extrapolation of the exponential
current decay curve back to the time (t
max
) when the current actually peaked (Ips
max
).
NOTE: The linear extrapolation should be based on the current waveform data over a 40-nanosecond period
beginning at t
max
(see Figure 2A).
Ips
max
(peak current maximum value). The highest current value measured.
NOTE: This value includes the overshoot or ringing components due to internal test simulator RLC parasitics
(see Figure 2A).
N-channel low parasitic HBM simulator. A simulator with similar in-specification waveforms for
both polarities and terminal A/B orientations when performing the procedure in Section 5.2.2 on a
pair of pins formed by a single pin and one pin of a pin group with N pins connected to N channels
of the tester.
no-connect pin. A package interconnect (pin, bump, or ball) not electrically connected to a die.
NOTE: In practice, some pins are labeled as “no-connect” but are actually connected to the die and, therefore,
should not be classified as no-connect pins for ESD testing.
non-socketed tester. An HBM simulator making contact with the device under test (DUT) pins (or
balls, lands, bumps, or die pads) with test probes rather than placing the DUT in a socket.
non-supply pin. A pin that is not categorized as a supply pin or a no-connect.
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JEDEC