ATtiny45/25/85微控制器特性与120强大指令详解

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ATtiny45是一款高性能、低功耗的AVR 8位微控制器，它基于先进的RISC架构设计，旨在提供高效的计算能力和优化的资源管理。这款微控制器的特点包括： 1. **高级指令集**：ATtiny45拥有120条强大的指令，大多数可以在单个时钟周期内执行，提高了代码执行效率。 2. **工作寄存器**：它配备了32个8位通用工作寄存器，支持全静态操作，有助于简化程序设计并提高响应速度。 3. **存储选项**： - **非易失性程序存储**：支持2/4/8KB的In-System Programmable（ISP）闪存，可用于在系统编程，可承受10,000次写入/擦除循环。 - **非易失性数据存储**：带有128/256/512B的ISP EEPROM，具有更高的耐用度，可以写入/擦除100,000次。 - **内部SRAM**：内置128/256/512B的随机访问内存，用于临时存储数据。 4. **安全功能**： - **定时器/计数器**：提供8位和高速8位定时器/计数器，分别带有预分频器和两个PWM通道。 - **高级PWM**：支持两个独立频率的PWM输出，有各自的输出比较寄存器。 - **死区时间发生器**：实现更精确的脉冲控制。 - **USI**：通用串行接口，带有起始条件检测功能，便于外部通信。 - **模拟数字转换器**（ADC）：具备10位分辨率，支持单端输入和一对可编程增益的差分输入通道，可用于温度测量。 - **看门狗定时器**：带有独立的片上振荡器，提供额外的系统稳定性保障。这些特性使得ATtiny45适用于各种低功耗、嵌入式应用，如无线传感器网络、电源管理、工业自动化和简单的控制任务，由于其小巧的尺寸和节能特性，特别适合电池供电设备。在设计项目时，开发者可以根据具体需求选择合适的存储容量，并充分利用其丰富的定时器和模拟功能来构建高效能的控制系统。

2586K–AVR–01/08

ATtiny25/45/85

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-

nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes.

The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

5.3 EEPROM Data Memory

The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a

separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register. For details see “Serial Downloading” on page

155.

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0DF/0x015F/0x025F

0x0060

Data Memory

clk

Data

ddress

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

2586K–AVR–01/08

ATtiny25/45/85

5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-

tered power supplies, V

is likely to rise or fall slowly on Power-up/down. This causes the

device for some period of time to run at a voltage lower than specified as minimum for the clock

frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the

user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn

bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write

operation. Both the erase and write cycle are done in one operation and the total programming

time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase and write opera-

tions are completed. While the device is busy with programming, it is not possible to do any

other EEPROM operations.

5.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possible to do the erase operations when the system allows doing time-critical

operations (typically after Power-up).

5.3.4 Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the

EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-

ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation

completes. While the device is busy programming, it is not possible to do any other EEPROM

operations.

5.3.5 Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit

remains set until the write operation completes. If the location to be written has not been erased

before write, the data that is stored must be considered as lost. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

2586K–AVR–01/08

ATtiny25/45/85

5.4 I/O Memory

The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 203.

All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers contain-

ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5 Register Description

5.5.1 EEARH and EEARL – EEPROM Address Register

• Bit 7:1 – Res6:0: Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny25/45/85.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address

in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be writ-

ten before the EEPROM may be accessed.

5.5.2 EEDR – EEPROM Data Register

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit 76543210

0x1F -------EEAR8EEARH

0x1E EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Bit 76543210

Read/Write RRRRRRRR/W

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

Initial ValueXXXXXXXX

Bit 76543210

0x1D EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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