Verilog实现RS编解码器BM_KES：纠错与初始化功能

`timescale 1ns/1ns
module BM_KES(S, clk, kes_init, kes_done, 
Lmd0, Lmd1, Lmd2, Lmd3, Lmd4, Lmd5, Lmd6, Lmd7, Lmd8, L, s_out);
parameter  t = 8, // t--The total number of errors that can be corrected
 N = 204, // N--Codeword length
 m = 8; // m--Extension of GF(2)

input    clk, kes_init;
input  [m-1:0]  S;
output [m-1:0]  L, Lmd0, Lmd1, Lmd2, Lmd3, Lmd4, Lmd5, Lmd6, Lmd7, Lmd8, s_out;
output kes_done;
reg    [m-1:0]  L;


//B(D) = B[2]*D^2 + B[1]*D + B[0]:Coefficients of Error Locator Polynomial 
reg [m-1:0] B[t:0];
reg [m-1:0] T[t:0], gama, delta, k; // gama--Intermediate variables; delta--Discrepency
reg [m-1:0] SSR[t*2:1]; // Registers of LFSR storing the syndrome 
wire [m-1:0] S_B[t:0]; // Product of (S*B)
integer counter;
reg [m-1:0] s_latched[t*2:1];
reg comput, kes_done;
always @(posedge clk/* or posedge kes_init*/)begin:BM_BLOCK
integer j;
if(kes_init)begin // Initial variables
delta <= 0;   
for(j=2; j<=t*2; j=j+1)
SSR[j] <= 0;
SSR[1] <= S;
counter <= 0;

end
else if(counter == t*2-1)begin
delta <= ((S_B[0]^S_B[1])^(S_B[2]^S_B[3]))^((S_B[4]^S_B[5])
^(S_B[6]^S_B[7]))^S_B[8]; // Updating of жд
for(j=1; j<=t*2-1; j=j+1)
SSR[j+1] <= SSR[j];
SSR[1] <= S;

for(j=1; j<=t*2; j=j+1) // Latch the input syndrome sequences
s_latched[j] <= SSR[j];

counter <= counter + 1;
        end
else if(counter <= t*2)begin
delta <= ((S_B[0]^S_B[1])^(S_B[2]^S_B[3]))^((S_B[4]^S_B[5])
^(S_B[6]^S_B[7]))^S_B[8]; // Updating of жд
for(j=1; j<=t*2-1; j=j+1)
SSR[j+1] <= SSR[j];
SSR[1] <= S;
counter <= counter + 1;
        end

end
FF_Mul S_x_B0(.B(SSR[1]), .A(B[0]), .P(S_B[0])); // FF multiplication of жд 
FF_Mul S_x_B1(.B(SSR[2]), .A(B[1]), .P(S_B[1]));
FF_Mul S_x_B2(.B(SSR[3]), .A(B[2]), .P(S_B[2]));
FF_Mul S_x_B3(.B(SSR[4]), .A(B[3]), .P(S_B[3]));
FF_Mul S_x_B4(.B(SSR[5]), .A(B[4]), .P(S_B[4]));
FF_Mul S_x_B5(.B(SSR[6]), .A(B[5]), .P(S_B[5]));
FF_Mul S_x_B6(.B(SSR[7]), .A(B[6]), .P(S_B[6]));