ARMv8架构手册：ARMv8-A设计详解

5星 · 超过95%的资源需积分: 50 168 浏览量更新于2024-07-18 1 收藏 38.11MB PDF 举报

ARMv8处理器手册是ARM公司为ARMv8-A架构设计的一份详细技术文档，它涵盖了ARMv8处理器架构的关键特性和实现细节。这份手册在2013年发布，版权归属于ARM Limited，并受到严格的版权保护，未经书面许可不得复制或实施其中的内容，除非有特定的授权声明。 ARMv8是ARM架构的一个重要版本，它标志着一个显著的技术飞跃，特别针对性能提升、指令集扩展以及向64位计算的转型。该手册主要关注以下几个方面： 1. **架构概述**：ARMv8架构包括了基本的处理器组件，如指令集、内存管理系统（MMU）、处理线程（SMP）和系统控制单元等，这些都是构建高性能系统的基石。 2. **64-bit支持**：ARMv8引入了64位（AArch64）架构，使得处理器可以处理更大的地址空间和更复杂的内存操作，提升了数据处理能力。 3. **NEON扩展**：NEON（单指令流多数据流）是ARM架构中的向量处理单元，v8版本进一步增强了其功能，支持更多的SIMD（Single Instruction Multiple Data）指令，用于并行计算和加速浮点运算。 4. **虚拟化与安全**：手册还讨论了ARMv8在虚拟化技术方面的改进，包括支持硬件辅助虚拟化（Hypervisor）、内存隔离和安全特性，以增强系统安全性。 5. **SMMU（System MMU）**：ARMv8引入了系统级内存管理单元，这有助于提高内存访问效率和安全性，通过统一的内存映射来简化系统设计。 6. **新的指令集**：ARMv8引入了诸如AArch64指令集，它包含了新的浮点、整数和控制转移指令，以适应现代计算需求。 7. **许可和版权声明**：手册明确指出，用户只能在同意不以任何形式滥用信息且无侵犯知识产权的前提下查阅，这表明ARM对于其技术的严谨态度和对知识产权的尊重。 8. **保密性质**：作为预览版的Beta文档，这意味着ARMv8处理器手册可能还在开发阶段，某些内容可能尚未公开或有待完善。 ARMv8处理器手册是设计者、开发者和研究人员深入了解ARMv8架构的必备参考资料，提供了深入理解和利用这一强大处理器架构的全面指南。通过阅读和遵循手册中的内容，用户能够优化性能、提升软件兼容性和安全性，从而在现代计算机系统设计中取得成功。

Preface

About this manual

Non-Confidential - Beta ID122413

About this manual

This manual describes the ARM

architecture v8, ARMv8. The architecture describes the operation of an

ARMv8-A Processing element (PE), and this manual includes descriptions of:

• The two Execution states, AArch64 and AArch32.

• The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the

ARM architecture.

— In AArch64 state, the A64 instruction set.

• The states that determine how a PE operates, including the current Exception level and Security state, and in

AArch32 state the PE mode.

• The Exception model.

• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.

• The memory model, that defines memory ordering and memory management. This manual covers a single

architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA).

• The programmers’ model, and its interfaces to System registers that control most PE and memory system

features, and provide status information.

• The Advanced SIMD and floating-point instructions, that provide high-performance:

— Single-precision and double-precision floating-point operations

— Conversions between double-precision, single-precision, and half-precision floating-point values.

— Integer, single-precision floating-point, and in A64, double-precision vector operations in all

instruction sets.

— Double-precision floating-point vector operations in the A64 instruction set.

• The security model, that provides two security states to support secure applications.

• The virtualization model, that support the virtualization of Non-secure operation.

• The Debug architecture, that provides software access to debug features.

This manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in

textual form. However, this manual is not a tutorial for ARM assembler language, nor does it describe ARM

assembler language, except at a very basic level. To make effective use of ARM assembler language, read the

documentation supplied with the assembler being used.

This manual is organized into parts:

Part A Provides an introduction to the ARMv8-A architecture, and an overview of the AArch64 and

AArch32 Execution states.

Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.

It describes the application level view of the programmers’ model and the memory model.

Part C Describes the A64 instruction set, that is available in the AArch64 Execution state. The descriptions

for each instruction also include the precise effects of each instruction when executed at EL0,

described as unprivileged execution, including any restrictions on its use, and how the effects of the

instruction differ at higher Exception levels. This information is of primary importance to authors

and users of compilers, assemblers, and other programs that generate ARM machine code.

Part D Describes the system level view of the AArch64 Execution state. It includes details of the System

registers, most of which are not accessible from EL0, and the system level view of the programmers’

model and the memory model. This part includes the description of self-hosted debug in AArch64

state.

Preface

About this manual

ID122413 Non-Confidential - Beta

Part E Describes the application level view of the AArch32 Execution state, meaning the view from the

EL0. It describes the application level view of the programmers’ model and the memory model.

Note

In AArch32 state, execution at EL0 is execution in User mode.

Part F Describes the T32 and A32 instruction sets, that are available in the AArch32 Execution state. These

instruction sets are backwards-compatible with earlier versions of the ARM architecture. This part

describes the precise effects of each instruction when executed in User mode, described as

unprivileged execution or execution at EL0, including any restrictions on its use, and how the effects

of the instruction differ at higher Exception levels. This information is of primary importance to

authors and users of compilers, assemblers, and other programs that generate ARM machine code.

Note

User mode is the only mode where software execution is unprivileged.

Part G Describes the system level view of the AArch32 Execution state, that is generally compatible with

earlier versions of the ARM architecture. This part includes details of the System registers, most of

which are not accessible from EL0, and the conceptual coprocessor interface to those registers. It

also describes the system level view of the programmers’ model and the memory model. This part

includes the description of self-hosted debug in AArch32 state.

Part H Describes the Debug architecture for external debug. This provides configuration, breakpoint and

watchpoint support, and a Debug Communications Channel (DCC) to a debug host.

Part I Describes additional features of the architecture that are not closely coupled to a processing element

(PE), and therefore are accessed through memory-mapped interfaces. Some of these features are

OPTIONAL.

Appendixes Provide additional information that is not part of the ARMv8 architectural requirements.

Preface

Using this manual

Non-Confidential - Beta ID122413

Using this manual

The information in this manual is organized into parts, as described in this section.

Part A, Introduction and Architecture Overview

Part A gives an overview of the ARMv8-A architecture profile, including its relationship to the other ARM PE

architectures. It introduces the terminology used to describe the architecture, and gives an overview of the

Executions states, AArch64 and AArch32. It contains the following chapter:

Chapter A1 Introduction to the ARMv8 Architecture

Read this for an introduction to the ARMv8 architecture.

Part B, The AArch64 Application Level Architecture

Part B describes the application level view of the architecture in AArch64 state. It contains the following chapters:

Chapter B1 The AArch64 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.

Chapter B2 The AArch64 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64

state. It includes information about ARM memory types, attributes, and memory access controls.

Part C, The A64 Instruction Set

Part C describes the A64 instruction set, that is used in AArch64 state. It contains the following chapters:

Chapter C1 The A64 Instruction Set

Read this for a description of the A64 instruction set and common instruction operation details.

Chapter C2 About the A64 Instruction Descriptions

Read this for a description of the A64 instruction descriptions.

Chapter C3 A64 Instruction Set Overview

Read this for an overview of the individual A64 instructions, that are divided into five functional

groups.

Chapter C4 A64 Instruction Set Encoding

Read this for a description of the A64 instruction set encoding.

Chapter C5 The A64 System Instruction Class

Read this for a description of the AArch64 system instructions and register descriptions, and the

system instruction class encoding space.

Chapter C6 A64 Base Instruction Descriptions

Read this for information on key aspects of the A64 base instructions and for descriptions of the

individual instructions, which are listed in alphabetical order.

Chapter C7 A64 Advanced SIMD and Floating-point Instruction Descriptions

Read this for information on key aspects of the A64 Advanced SIMD and floating-point instructions

and for descriptions of the individual instructions, which are listed in alphabetical order.

Preface

Using this manual

ID122413 Non-Confidential - Beta

Part D, The AArch64 System Level Architecture

Part D describes the AArch64 the system level view of the architecture. It contains the following chapters:

Chapter D1 The AArch64 System Level Programmers’ Model

Read this for a description of the AArch64 system level view of the programmers’ model.

Chapter D2 AArch64 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch64 state.

Chapter D3 The AArch64 System Level Memory Model

Read this for a description of the AArch64 system level view of the general features of the memory

system.

Chapter D4 The AArch64 Virtual Memory System Architecture

Read this for a system level view of the AArch64 Virtual Memory System Architecture (VMSA),

the memory system architecture of an ARMv8 implementation that is executing in AArch64 state.

Chapter D5 The Performance Monitors Extension

Read this for a description of an implementation of the ARM Performance Monitors, that are an

optional non-invasive debug component.

Chapter D6 The Generic Timer

Read this for a description of an implementation of the ARM Generic Timer, that is an optional

extension to an ARMv8 implementation.

Chapter D7 AArch64 System Register Descriptions

Read this for an introduction to, and description of, each of the AArch64 system registers.

Part E, The AArch32 Application Level Architecture

Part E describes the AArch32 application level view of the architecture. It contains the following chapters:

Chapter E1 The AArch32 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch32 state. It describes execution at EL0 when EL0 is using AArch32 state.

Chapter E2 The AArch32 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch32 state. It describes the memory model for execution in EL0 when EL0 is using AArch32

state. It includes information about ARM memory types, attributes, and memory access controls.

Part F, The AArch32 Instruction Sets

Part F describes the T32 and A32 instruction sets, that are used in AArch32 state. It contains the following chapters:

Chapter F1 The AArch32 Instruction Sets Overview

Read this for an overview of the T32 and A32 instruction sets.

Chapter F2 About the T32 and A32 Instruction Descriptions

Read this for a description of the T32 and A32 instructions.

Chapter F3 T32 Base Instruction Set Encoding

Read this for an introduction to the T32 instruction set and a description of how the T32 instruction

set uses the ARM programmers’ model.

Chapter F4 A32 Base Instruction Set Encoding

Read this for a description of the A32 base instruction set encoding.

Preface

Using this manual

Non-Confidential - Beta ID122413

Chapter F5 T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings

Read this for an overview of the T32 and A32 Advanced SIMD and floating-point instruction sets.

Chapter F6 ARMv8 Changes to the T32 and A32 Instruction Sets

Read this for a summary of the changes that are introduced to the T32 and A32 instruction sets in

ARMv8.

Chapter F7 T32 and A32 Base Instruction Set Instruction Descriptions

Read this for a description of each T32 and A32 base instruction.

Chapter F8 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions

Read this for a description of each T32 and A32 Advanced SIMD and floating-point instruction.

Part G, The AArch32 System Level Architecture

Part G describes the AArch32 system level view of the architecture. It contains the following chapters:

Chapter G1 The AArch32 System Level Programmers’ Model

Read this for a description of the AArch32 system level view of the programmers’ model for

execution in an Exception level that is using AArch32.

Chapter G2 AArch32 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch32 state.

Chapter G3 The AArch32 System Level Memory Model

Read this for a system level view of the general features of the memory system.

Chapter G4 The AArch32 Virtual Memory System Architecture

Read this for a description of the AArch32 Virtual Memory System Architecture (VMSA).

Chapter G5 AArch32 System Register Descriptions

Read this for a description of each of the AArch32 system registers.

Part H, External Debug

Part H describes the architecture for external debug. It contains the following chapters:

Chapter H1 Introduction to External Debug

Read this for an introduction to external debug, and a definition of the scope of this part of the

manual.

Chapter H2 Debug State

Read this for a description of debug state, which the PE might enter as the result of a Halting debug

event.

Chapter H3 Halting Debug Events

Read this for a description of the external debug events referred to as Halting debug events.

Chapter H4 The Debug Communication Channel and Instruction Transfer Register

Read this for a description of the communication between a debugger and the PE debug logic using

the Debug Communications Channel and the Instruction Transfer register.

Chapter H5 The Embedded Cross Trigger Interface

Read this for a description of the embedded cross-trigger interface.

Chapter H6 Debug Reset and Powerdown Support

Read this for a description of reset and powerdown support in the Debug architecture.

剩余5241页未读，继续阅读

wisent

粉丝: 0
资源: 7

ARMv8架构手册：ARMv8-A设计详解

ARMv8-A架构参考手册_架构参考手册_ARMv8-A_

ARM Architecture Reference Manual for ARMv8-A

arm v8手册，仅供自己下载

armv8架构中文手册

arm庐 architecture reference manual armv8, for armv8-a architecture

armv8汇编语言官方手册中文

armv8.6芯片手册

arm architecture reference manual armv8 for armv8-a architecture profile

armv8 architecture reference manua

arm architecture reference manual for armv8

最新资源