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首页全志A10处理器手册:CPU与GPU特性详解
全志A10处理器手册:CPU与GPU特性详解
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"全志A10手册"
全志A10手册是针对全志科技公司(Aliwinner Technology Co., Ltd.)的一款处理器芯片——A10的详细技术文档。手册覆盖了芯片的各项技术特性、引脚描述、架构设计以及启动模式等多个方面。以下是手册中的关键知识点:
1. 特性介绍:
- CPU: A10采用的是ARMCortex™-A8内核,基于ARMv7指令集架构,提供了高性能的计算能力。
- GPU: 集成了Mali-400图形处理单元,支持2D/3D图形处理,适用于多媒体应用。
- VPU: 视频处理单元,增强了视频编码和解码的能力。
- 显示处理能力: 能够处理复杂的图像显示任务,适应多种分辨率的显示需求。
- 显示输出能力: 支持多路显示输出,如HDMI、LVDS等接口。
- 图像输入能力: 提供了处理各种图像输入源的能力。
- 内存: 使用同步动态随机访问内存(SDRAM),与系统总线同步,确保高效的数据存取。
- 外设: 包括各种接口,如USB、GPIO、I2C、SPI等,方便扩展硬件功能。
- 系统: 设计考虑了系统的稳定性和兼容性,适合嵌入式设备应用。
- 安全: 内置安全特性,确保数据和系统的安全性。
- 封装: 提供了合适的芯片封装形式,便于集成到硬件设计中。
2. 引脚描述:
- 引脚布局表: 显示了芯片上各个引脚的位置,帮助开发者进行硬件布局。
- 引脚详细描述: 对每个引脚的功能和用法进行了详细解释,指导硬件连接。
3. 架构设计:
- 总体模块图: 展示了A10芯片的整体架构,包括CPU、GPU、内存控制器和其他外围模块的相互关系。
- 内存映射: 描述了内部存储器空间的分配和组织,对于编程和内存管理至关重要。
4. 启动模式:
- 详细介绍了芯片的不同启动方式,可能包括从闪存、外部Nor Flash、SD卡等多种启动介质选择。
5. 版本历史:
- 手册经过多次修订,例如V1.00的初始版本,V1.01的格式调整,V1.10对音频编解码的修改,以及V1.20对USB部分的更新。
全志A10手册提供了全面的技术信息,是开发基于A10芯片产品的工程师的重要参考资料。它涵盖了从硬件设计到软件开发的多个层面,有助于理解和优化基于A10平台的系统性能。
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 15
2012-04-09
30.3.18. PB Pull Register 1 .................................................................................................................. 298
30.3.19. PC Configure Register 0 ........................................................................................................ 298
30.3.20. PC Configure Register 1 ........................................................................................................ 299
30.3.21. PC Configure Register 2 ........................................................................................................ 301
30.3.22. PC Configure Register 3 ........................................................................................................ 302
30.3.23. PC Data Register .................................................................................................................... 302
30.3.24. PC Multi-Driving Register 0 .................................................................................................. 303
30.3.25. PC Multi-Driving Register 1 .................................................................................................. 303
30.3.26. PC Pull Register 0 .................................................................................................................. 303
30.3.27. PC Pull Register 1 .................................................................................................................. 303
30.3.28. PD Configure Register 0 ........................................................................................................ 304
30.3.29. PD Configure Register 1 ........................................................................................................ 305
30.3.30. PD Configure Register 2 ........................................................................................................ 306
30.3.31. PD Configure Register 3 ........................................................................................................ 307
30.3.32. PD Data Register .................................................................................................................... 308
30.3.33. PD Multi-Driving Register 0 .................................................................................................. 309
30.3.34. PD Multi-Driving Register 1 .................................................................................................. 309
30.3.35. PD Pull Register 0 .................................................................................................................. 309
30.3.36. PD Pull Register 1 .................................................................................................................. 309
30.3.37. PE Configure Register 0 ......................................................................................................... 310
30.3.38. PE Configure Register 1 ......................................................................................................... 311
30.3.39. PE Configure Register 2 ......................................................................................................... 312
30.3.40. PE Configure Register 3 ......................................................................................................... 312
30.3.41. PE Data Register .................................................................................................................... 312
30.3.42. PE Multi-Driving Register 0 .................................................................................................. 312
30.3.43. PE Multi-Driving Register 1 .................................................................................................. 313
30.3.44. PE Pull Register 0 .................................................................................................................. 313
30.3.45. PE Pull Register 1 .................................................................................................................. 313
30.3.46. PF Configure Register 0 ......................................................................................................... 313
30.3.47. PF Configure Register 1 ......................................................................................................... 314
30.3.48. PF Configure Register 2 ......................................................................................................... 314
30.3.49. PF Configure Register 3 ......................................................................................................... 315
30.3.50. PF Data Register .................................................................................................................... 315
30.3.51. PF Multi-Driving Register 0 .................................................................................................. 315
30.3.52. PF Multi-Driving Register 1 .................................................................................................. 315
30.3.53. PF Pull Register 0................................................................................................................... 316
30.3.54. PF Pull Register 1................................................................................................................... 316
30.3.55. PG Configure Register 0 ........................................................................................................ 316
30.3.56. PG Configure Register 1 ........................................................................................................ 317
30.3.57. PG Configure Register 2 ........................................................................................................ 318
30.3.58. PG Configure Register 3 ........................................................................................................ 318
30.3.59. PG Data Register .................................................................................................................... 318
30.3.60. PG Multi-Driving Register 0 .................................................................................................. 319
30.3.61. PG Multi-Driving Register 1 .................................................................................................. 319
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 16
2012-04-09
30.3.62. PG Pull Register 0 .................................................................................................................. 319
30.3.63. PG Pull Register 1 .................................................................................................................. 319
30.3.64. PH Configure Register 0 ........................................................................................................ 320
30.3.65. PH Configure Register 1 ........................................................................................................ 321
30.3.66. PH Configure Register 2 ........................................................................................................ 322
30.3.67. PH Configure Register 3 ........................................................................................................ 323
30.3.68. PH Data Register .................................................................................................................... 324
30.3.69. PH Multi-Driving Register 0 .................................................................................................. 325
30.3.70. PH Multi-Driving Register 1 .................................................................................................. 325
30.3.71. PH Pull Register 0 .................................................................................................................. 325
30.3.72. PH Pull Register 1 .................................................................................................................. 325
30.3.73. PI Configure Register 0 .......................................................................................................... 326
30.3.74. PI Configure Register 1 .......................................................................................................... 327
30.3.75. PI Configure Register 2 .......................................................................................................... 328
30.3.76. PI Configure Register 3 .......................................................................................................... 329
30.3.77. PI Data Register ..................................................................................................................... 329
30.3.78. PI Multi-Driving Register 0 ................................................................................................... 330
30.3.79. PI Multi-Driving Register 1 ................................................................................................... 330
30.3.80. PI Pull Register 0 ................................................................................................................... 330
30.3.81. PI Pull Register 1 ................................................................................................................... 330
30.3.82. PIO Interrupt Configure Register 0 ........................................................................................ 331
30.3.83. PIO Interrupt Configure Register 1 ........................................................................................ 331
30.3.84. PIO Interrupt Configure Register 2 ........................................................................................ 331
30.3.85. PIO Interrupt Configure Register 3 ........................................................................................ 332
30.3.86. PIO Interrupt Control Register ............................................................................................... 332
30.3.87. PIO Interrupt Status Register ................................................................................................. 332
30.3.88. PIO Interrupt Debounce Register ........................................................................................... 333
31. CSI0 with ISP FE ................................................................................................................................. 334
31.1. Overview ........................................................................................................................................ 334
31.2. Feature ............................................................................................................................................ 334
31.2.1. CSI ......................................................................................................................................... 334
31.2.2. ISP FE .................................................................................................................................... 334
31.3. Block diagram ................................................................................................................................ 335
31.3.1. CSI data ports ......................................................................................................................... 335
31.4. Timing ............................................................................................................................................ 335
31.4.1. CSI timing .............................................................................................................................. 335
31.4.2. 16bit YUV422 Timing ........................................................................................................... 336
31.4.3. CCIR656 2 channel Timing ................................................................................................... 336
31.4.4. CCIR656 4 channel Timing ................................................................................................... 337
31.4.5. CCIR656 Header Code .......................................................................................................... 337
31.5. CSI0 Register List .......................................................................................................................... 338
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 17
2012-04-09
31.6. CSI0 Register Description.............................................................................................................. 343
31.6.1. CSI Enable Register ............................................................................................................... 343
31.6.2. CSI configuration register ...................................................................................................... 343
31.6.3. CSI capture control register ................................................................................................... 345
31.6.4. CSI horizontal scale register .................................................................................................. 346
31.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 346
31.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 346
31.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 347
31.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 347
31.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 347
31.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 347
31.6.11. CSI Channel_0 output buffer control register ........................................................................ 347
31.6.12. CSI Channel_0 status register ................................................................................................ 348
31.6.13. CSI Channel_0 interrupt enable register ................................................................................ 349
31.6.14. CSI Channel_0 interrupt status register ................................................................................. 350
31.6.15. CSI Channel_0 horizontal size register .................................................................................. 350
31.6.16. CSI Channel_0 vertical size register ...................................................................................... 350
31.6.17. CSI Channel_0 buffer length register ..................................................................................... 351
31.6.18. CSI Channel_1 FIFO 0 output buffer-A address register ....................................................... 351
31.6.19. CSI Channel_1 FIFO 0 output buffer-B address register ....................................................... 351
31.6.20. CSI Channel_1 FIFO 1 output buffer-A address register ....................................................... 351
31.6.21. CSI Channel_1 FIFO 1 output buffer-B address register ....................................................... 352
31.6.22. CSI Channel_1 FIFO 2 output buffer-A address register ....................................................... 352
31.6.23. CSI Channel_1 FIFO 2 output buffer-B address register ....................................................... 352
31.6.24. CSI Channel_1 output buffer control register ........................................................................ 352
31.6.25. CSI Channel_1 status register ................................................................................................ 353
31.6.26. CSI Channel_1 interrupt enable register ................................................................................ 353
31.6.27. CSI Channel_1 interrupt status register ................................................................................. 354
31.6.28. CSI Channel_1 horizontal size register .................................................................................. 355
31.6.29. CSI Channel_1 vertical size register ...................................................................................... 355
31.6.30. CSI Channel_1 buffer length register ..................................................................................... 356
31.6.31. CSI Channel_2 FIFO 0 output buffer-A address register ....................................................... 356
31.6.32. CSI Channel_2 FIFO 0 output buffer-B address register ....................................................... 356
31.6.33. CSI Channel_2 FIFO 1 output buffer-A address register ....................................................... 356
31.6.34. CSI Channel_2 FIFO 1 output buffer-B address register ....................................................... 356
31.6.35. CSI Channel_2 FIFO 2 output buffer-A address register ....................................................... 357
31.6.36. CSI Channel_2 FIFO 2 output buffer-B address register ....................................................... 357
31.6.37. CSI Channel_2 output buffer control register ........................................................................ 357
31.6.38. CSI Channel_2 status register ................................................................................................ 358
31.6.39. CSI Channel_2 interrupt enable register ................................................................................ 358
31.6.40. CSI Channel_2 interrupt status register ................................................................................. 359
31.6.41. CSI Channel_2 horizontal size register .................................................................................. 360
31.6.42. CSI Channel_2 vertical size register ...................................................................................... 360
31.6.43. CSI Channel_2 buffer length register ..................................................................................... 360
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 18
2012-04-09
31.6.44. CSI Channel_3 FIFO 0 output buffer-A address register ....................................................... 361
31.6.45. CSI Channel_3 FIFO 0 output buffer-B address register ....................................................... 361
31.6.46. CSI Channel_3 FIFO 1 output buffer-A address register ....................................................... 361
31.6.47. CSI Channel_3 FIFO 1 output buffer-B address register ....................................................... 361
31.6.48. CSI Channel_3 FIFO 2 output buffer-A address register ....................................................... 361
31.6.49. CSI Channel_3 FIFO 2 output buffer-B address register ....................................................... 362
31.6.50. CSI Channel_3 output buffer control register ........................................................................ 362
31.6.51. CSI Channel_3 status register ................................................................................................ 362
31.6.52. CSI Channel_3 interrupt enable register ................................................................................ 363
31.6.53. CSI Channel_3 interrupt status register ................................................................................. 364
31.6.54. CSI Channel_3 horizontal size register .................................................................................. 364
31.6.55. CSI Channel_3 vertical size register ...................................................................................... 365
31.6.56. CSI Channel_3 buffer length register ..................................................................................... 365
31.6.57. ISP Enable register ................................................................................................................. 365
31.6.58. ISP Mode register ................................................................................................................... 366
31.6.59. ISP OBC Image Black size register........................................................................................ 367
31.6.60. ISP OBC Image Valid size register ........................................................................................ 367
31.6.61. ISP OBC Image Start register................................................................................................. 367
31.6.62. ISP OBC configuration register ............................................................................................. 368
31.6.63. ISP Horizontal OBC window start register ............................................................................ 368
31.6.64. ISP Vertical OBC window start register ................................................................................. 369
31.6.65. ISP Vertical OBC parameter register ...................................................................................... 369
31.6.66. ISP OBC fixed value register ................................................................................................. 369
31.6.67. ISP OBC offset register .......................................................................................................... 370
31.6.68. ISP OBC clamp value register ................................................................................................ 370
31.6.69. ISP LSC configuration register .............................................................................................. 370
31.6.70. ISP LSC gain factor address register ...................................................................................... 371
31.6.71. ISP LSC gain factor address length register ........................................................................... 371
31.6.72. ISP Offset register .................................................................................................................. 371
31.6.73. ISP Gain Factor register ......................................................................................................... 371
31.6.74. ISP Dark Frame Enable register ............................................................................................. 372
31.6.75. ISP Dark Frame buffer address register ................................................................................. 372
31.6.76. ISP Dark Frame buffer address length register ...................................................................... 372
31.6.77. ISP luma DC subtraction value register ................................................................................. 373
31.6.78. ISP H3A Median filter threshold register ............................................................................... 373
31.6.79. ISP AF window number register ............................................................................................ 373
31.6.80. ISP AF window size register .................................................................................................. 374
31.6.81. ISP AF window start register.................................................................................................. 374
31.6.82. ISP AF configuration register ................................................................................................. 374
31.6.83. ISP AF filter parameter 0 register ........................................................................................... 375
31.6.84. ISP AF filter parameter 1 register ........................................................................................... 375
31.6.85. ISP AF filter parameter 2 register ........................................................................................... 375
31.6.86. ISP AWBE window number register ...................................................................................... 376
31.6.87. ISP AWBE window size register ............................................................................................ 376
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 19
2012-04-09
31.6.88. ISP AWBE window start register ........................................................................................... 376
31.6.89. ISP AWBE configuration register .......................................................................................... 377
31.6.90. ISP Histogram region 0 window size register ........................................................................ 377
31.6.91. ISP Histogram region 0 window start register ....................................................................... 377
31.6.92. ISP Histogram region 1 window size register ........................................................................ 378
31.6.93. ISP Histogram region 1 window start register ....................................................................... 378
31.6.94. ISP Histogram region 2 window size register ........................................................................ 378
31.6.95. ISP Histogram region 2 window start register ....................................................................... 379
31.6.96. ISP Histogram region 3 window size register ........................................................................ 379
31.6.97. ISP Histogram region 3 window start register ....................................................................... 379
31.6.98. ISP 3A Statistics output address register ................................................................................ 380
31.6.99. ISP LUT Defect Correction configuration register ................................................................ 380
31.6.100. ISP LUT Defect Correction address register .......................................................................... 380
31.6.101. ISP FE Y/Raw Output address length register ....................................................................... 381
31.6.102. SP FE Y/Raw Output address register .................................................................................... 381
31.6.103. ISP interrupt enable register ................................................................................................... 381
31.6.104. ISP interrupt status register .................................................................................................... 382
31.6.105. ISP FE CbCr Output address length register .......................................................................... 382
31.6.106. ISP FE CbCr Output address register ..................................................................................... 383
32. CSI1 ....................................................................................................................................................... 384
32.1. Overview ........................................................................................................................................ 384
32.2. Block diagram ................................................................................................................................ 384
32.3. CSI data ports ................................................................................................................................. 385
32.4. Timing ............................................................................................................................................ 385
32.4.1. CSI timing .............................................................................................................................. 385
32.5. CSI1 Registers List ........................................................................................................................ 385
32.6. CSI1 Register Description.............................................................................................................. 386
32.6.1. CSI Enable Register ............................................................................................................... 386
32.6.2. CSI configuration register ...................................................................................................... 387
32.6.3. CSI capture control register ................................................................................................... 389
32.6.4. CSI horizontal scale register .................................................................................................. 389
32.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 390
32.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 390
32.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 390
32.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 391
32.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 391
32.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 391
32.6.11. CSI Channel_0 output buffer control register ........................................................................ 391
32.6.12. CSI Channel_0 status register ................................................................................................ 392
32.6.13. CSI Channel_0 interrupt enable register ................................................................................ 393
32.6.14. CSI Channel_0 interrupt status register ................................................................................. 394
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