MT9V034: 1/3英寸VGADIS传感器技术规格

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本文档是关于MT9V034型号的1/3英寸宽视野CMOS数字图像传感器的数据手册，由Aptina Imaging Corporation发布。该产品具有以下主要特性： 1. **Digital Clarity® CMOS技术**：采用先进的CMOS成像技术，确保图像的清晰度和质量，这是Aptina的核心竞争力。 2. **阵列格式**：MT9V034传感器具有宽视野格式，分辨率为752像素宽x 480像素高（360,960个像素），适合各种高分辨率应用。 3. **TrueSNAP™全局快门**：每个像素都有独立的光敏二极管，实现同时集成和读出，提供无延迟的图像捕获，这对于对实时性和一致性有高要求的应用尤其重要。 4. **颜色选项**：支持黑白和增强近红外(NIR)性能，使其适用于使用非可见光照明的应用场景，如夜间或低光条件下的监控。 5. **读出模式**：提供两种模式——逐行扫描（progressive）和交错扫描（interlaced），以适应不同的数据传输需求。 6. **高 shutter效率**：超过99%的快门效率意味着传感器能最大限度地捕捉光线，减少丢失的影像信息。 7. **接口设计**：采用简单的双线串行接口，简化了系统设计，减少了所需的连接器和线路数量。 8. **实时曝光控制**：支持实时曝光切换，配备双寄存器集，便于灵活调整曝光时间和图像处理。 9. **注册锁定功能**：允许用户锁定特定的图像区域或模式，提高图像稳定性和一致性。 10. **窗口尺寸可编程**：用户可以根据需求选择不同格式，如QVGA、CIF或QCIF，数据速率可以根据实际应用场景独立调整。最后，要获取最新的规格和更新信息，用户应访问Aptina Imaging Corporation的官方网站www.aptina.com，以确保始终了解产品的最新状态。在整个文档中，所有的产品规格和描述都可能在未经通知的情况下由Aptina进行更改，因此保持关注官方资料是至关重要的。

PDF: 09005aef8366edcb/Source: 09005aef8366ede5 Aptina Imaging reserves the right to change products or specifications without notice.

MT9V034_DS - Rev. A 10/08 EN

MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Format

Aptina Confidential and Proprietary

Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to

Figure 7 on page 13). The recommended master clock frequency is 26.66 MHz. The

vertical blanking and the total frame time equations assume that the integration time

(Coarse Shutter Width plus Fine Shutter Width) is less than the number of active rows

plus the blanking rows minus the overhead rows:

Window Height + Vertical Blanking – 2 (EQ 1)

If this is not the case, the number of integration rows must be used instead to determine

the frame time, as shown in Table 5. In this example it is assumed that the Coarse Shutter

Width Control is programmed with 523 rows, and the Fine Shutter Width Total is zero.

For Simultaneous mode, if the exposure time registers (Coarse Shutter Width Total plus

Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time

is internally extended automatically to adjust for the additional integration time

required. This extended value is not written back to the vertical blanking registers. The

Vertical Blank register can be used to adjust frame-to-frame readout time. This register

does not affect the exposure time but it may extend the readout time.

Notes: 1. The MT9V034 uses column parallel analog-digital converters, thus short row timing is not possible.

The minimum total row time is 690 columns (horizontal width + horizontal blanking). The mini-

mum horizontal blanking is 61. When the window width is set below 627, horizontal blanking

must be increased.

A+Q Row time Context A: R0x04 + R0x05

Context B: R0xCC + R0xCD

846 pixel clocks

= 846 master

= 31.72μs

V Vertical blanking Context A: (R0x06) x (A + Q) + 4

Context B: (R0xCE) x (A + Q) + 4

38,074 pixel clocks

= 38,074 master

= 1.43ms

Nrows x (A + Q) Frame valid time Context A: (R0x03) × (A + Q)

Context B: (R0xCB) x (A + Q)

406,080 pixel clocks

= 406,080 master

= 15.23ms

F Total frame time V + (Nrows x (A + Q)) 444,154 pixel clocks

= 444,154 master

= 16.66ms

Table 5: Frame Time—Long Integration Time

Parameter Name

Equation

(Number of Master Clock Cycles)

Default Timing

at 26.66 MHz

V’

Vertical blanking (long

integration time)

Context A: (R0x0B + 2 - R0x03) × (A + Q) + R0xD5 + 4

Context B: (R0xD2 + 2 - R0xCB) x (A + Q) + R0xD8 + 4

38,074 pixel clocks

= 38,074 master

= 1.43ms

Total frame time (long

integration time)

Context A: (R0x0B + 2) × (A + Q) + R0xD5 + 4

Context B: (R0xD2 + 2) x (A + Q) + R0xD8 + 4

444,154 pixel clocks

= 444,154 master

= 16.66ms

Table 4: Frame Time (continued)

Parameter Name Equation Default Timing at 26.66 MHz

PDF: 09005aef8366edcb/Source: 09005aef8366ede5 Aptina Imaging reserves the right to change products or specifications without notice.

MT9V034_DS - Rev. A 10/08 EN

MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor

Serial Bus Description

Aptina Confidential and Proprietary

Serial Bus Description

Registers are written to and read from the MT9V034 through the two-wire serial inter-

face bus. The MT9V034 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0

and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is

transferred into the MT9V034 and out through the serial data (S

DATA) line. The SDATA

line is pulled up to V

DD off-chip by a 1.5KΩ resistor. Either the slave or master device can

pull the S

DATA line down—the serial interface protocol determines which device is

allowed to pull the S

DATA line down at any given time. The registers are 16-bit wide, and

can be accessed through 16- or 8-bit two-wire serial interface sequences.

Protocol

The two-wire serial interface defines several different transmission codes, as shown in

the following sequence:

1. a start bit

2. the slave device 8-bit address

3. a(n) (no) acknowledge bit

4. an 8-bit message

5. a stop bit

Start Bit

The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line

is HIGH.

Slave Address

The 8-bit address of a two-wire serial interface device consists of 7 bits of address and

1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indi-

cates read mode. As indicated above, the MT9V034 allows four possible slave addresses

determined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1.

Acknowledge Bit

The master generates the acknowledge clock pulse. The transmitter (which is the master

when writing, or the slave when reading) releases the data line, and the receiver indi-

cates an acknowledge bit by pulling the data line LOW during the acknowledge clock

pulse.

No-Acknowledge Bit

The no-acknowledge bit is generated when the data line is not pulled down by the

receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate

a read sequence.

Stop Bit

The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line

is HIGH.

PDF: 09005aef8366edcb/Source: 09005aef8366ede5 Aptina Imaging reserves the right to change products or specifications without notice.

MT9V034_DS - Rev. A 10/08 EN

MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor

Serial Bus Description

Aptina Confidential and Proprietary

Sequence

A typical READ or WRITE sequence begins by the master sending a start bit. After the

start bit, the master sends the slave device’s 8-bit address. The last bit of the address

determines if the request is a read or a write, where a “0” indicates a WRITE and a “1”

indicates a READ. The slave device acknowledges its address by sending an acknowledge

bit back to the master.

If the request was a WRITE, the master then transfers the 8-bit register address to which

a WRITE should take place. The slave sends an acknowledge bit to indicate that the

with the slave sending an acknowledge bit after each 8 bits. The MT9V034 uses 16-bit

data for its internal registers, thus requiring two 8-bit transfers to write to one register.

After 16 bits are transferred, the register address is automatically incremented, so that

the next 16 bits are written to the next register address. The master stops writing by

sending a start or stop bit.

A typical READ sequence is executed as follows. First the master sends the write mode

slave address and 8-bit register address, just as in the write request. The master then

sends a start bit and the read mode slave address. The master then clocks out the register

data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The

transfer is stopped when the master sends a no-acknowledge bit. The MT9V034 allows

for 8-bit data transfers through the two-wire serial interface by writing (or reading) the

most significant 8 bits to the register and then writing (or reading) the least significant 8

bits to Byte-Wise Address register (0x0F0).

Bus Idle State

The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-

ated with a start bit, and the bus is released with a stop bit. Only the master can generate

the start and stop bits.

Data Bit Transfer

One data bit is transferred during each clock pulse. The two-wire serial interface clock

pulse is provided by the master. The data must be stable during the HIGH period of the

serial clock—it can only change when the two-wire serial interface clock is LOW. Data is

transferred 8 bits at a time, followed by an acknowledge bit.

Table 6: Slave Address Modes

{S_CTRL_ADR1, S_CTRL_ADR0} Slave Address Write/Read Mode

00 0x90 Write

0x91 Read

01 0x98 Write

0x99 Read

10 0xB0 Write

0xB1 Read

11 0xB8 Write

0xB9 Read

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