24GHz低功耗低相噪PLL频率合成器：常数KVCO适用于60GHz无线应用

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本文介绍了一种针对60GHz无线应用的24GHz低功耗、低相位噪声的积分型锁相环频率合成器。设计的关键在于采用了尾反馈技术改进了相位噪声性能，通过集成一个开关电抗器阵列与开关电容阵列，有效地补偿了KVCO（电压控制振荡器）在不同频段的电压变化。为了实现极低的功耗，文中特别强调了CML预分频器的精心优化，使得当VCO缓冲器关闭时，PLL仍能正常工作。设计采用的A24GHz VCO利用了尾反馈，通过调节尾电流来控制相位噪声，达到了-102分贝赫兹（dBc/Hz）的优异性能，在1MHz的偏移下。同时，该VCO的调谐范围超过16%，确保了在宽频率范围内KVCO的稳定性。在闭环模式下，整个PLL在规定频带内的集成相位误差仅为3.3度的根均方（rms），从100kHz到100MHz的频率范围内表现出出色的性能。设计者还注重了整体功耗的管理，整体制成的PLL在标准90纳米工艺下实现，其总功耗仅有26毫瓦（mW），显示出在追求高频率应用的同时，对低功耗设计的高度重视。这种24GHz PLL频率合成器的开发对于满足60GHz无线通信系统的高性能和低功耗需求具有重要意义，为无线传输设备如接收器提供了一个理想的选择。

A 24GHz Low Power and Low Phase Noise PLL

Frequency Synthesizer with Constant K

VCO

for

60GHz Wireless Applications

Jun Luo, Lei Zhang, Member, IEEE, Li Zhang, Yan Wang and Zhiping Yu, Fellow, IEEE

Abstract —In this paper, a fully integrated 24GHz

integer-N PLL for a 60GHz wireless transceiver is presented.

A VCO with tail-feedback technique is used to improve the

phase noise by modulating the tail current, and a switched

varactor array is also adopted together with a switched

capacitor array to compensate the variation of K

VCO

over

different bands. Moreover, benefiting from the careful

optimization of CML pre-scaling divider, the PLL operates

correctly when VCO buffer is turned off, coming up with an

extremely low power. The whole PLL is fabricated in

standard 90-nm process. Measurement shows that the VCO

achieves a phase noise of -102dBc/Hz@1MHz offset with a

tuning range of over 16%. The K

VCO

variation over all bands

is less than 16%. In close-loop operation mode the PLL

shows an integrated phase error of 3.3°rms (from 100kHz to

100MHz) over prescribed frequency bands, and a total power

dissipation of only 26mW.

Index Terms —PLL, VCO, low power, phase noise, 24GHz.

I. INTRODUCTION

The wide unlicensed 7GHz bandwidth around 60GHz

enables high speed wireless communication with multiple

Gbps data rate, which has increasingly drawn attentions

from both academia and industry [1]. Phase-locked Loop

(PLL), is a key building block for frequency synthesis in

most of the transceivers. A voltage-controlled oscillator

(VCO) operating at high frequency consumes a large

power and suffers from a narrow tuning range, especially

for millimeter-wave (mm-wave) applications [2].

Moreover, a large power is also consumed by the pre-

scaling frequency dividers interfacing with VCO in a PLL

system. Considering the power consumption and local

oscillation (LO) distribution, a 24GHz PLL serving for

LO frequency synthesis is employed in a super-heterodyne

60GHz transceiver, in which the first and second LO

signals are generated by a doubler and a divider following

the PLL, respectively.

Even at 24GHz band, PLL is still power hungry. There

are many reported works on the low power design of VCO

and pre-scaling dividers at mm-wave frequency [3].

However, few work focuses on the co-optimization of the

feed-back chain composed of VCO buffer and the first

pre-scaling divider which is power hungry. Moreover, due

to the PLL stability requirement over a wide band, e.g.

60GHz applications, maintaining a constant loop

bandwidth (LBW) is mandatory, which calls for a constant

VCO

. Although it has drawn attentions in low frequency

designs [4], few work has been reported in mm-wave

PLLs.

In this paper, a 24GHz 4 channel integer-N PLL is

designed. On one hand, a switched varactor array is

adopted together a switched capacitor array to compensate

the variation of K

VCO

over different bands, and tail-

feedback in VCO is also incorporated to improve the

phase noise. On the other hand, analysis and design of

CML divider based on second-order approximation is

proposed for power and operation range co-optimization.

Measurement shows that even the VCO buffer is turned

off, the PLL can still work correctly, coming up with an

extremely low power.

This paper is organized as follows: Section II discusses

the circuit design considerations and proposed techniques

of the PLL. Section III presents the measurement results,

and finally the conclusions are drawn in Section IV.

PFD

CML_

MMD_DIV_27

~30

Fref=108MHz

CML_

CML

Buf_for_test

23.5GHz~28.2GHz

VCO_Buf

Fig. 1. Proposed 24GHz integer-N PLL with frequency planning.

II. CIRCUIT DESIGN OF THE PLL SYNTHESIZER

The 24GHz PLL is designed with an integer-N

topology for the purpose of simple tuning and superior

phase noise as shown in Fig. 1. A VCO buffer, whose

supply voltage can be tuned, is connected to the VCO,

with a tuning range from 23.5GHz to 28.2GHz. Three

CML divide-by-2 dividers, serving for pre-scaling, are

This work is supported by National 863 Program of Chin

2011AA010202 and 2015AA011307, National Natural Science

Foundation of China under grants 61101001 and 61204026, an

Tsinghua University Initiative Scientific Research Program.

The authors are with Institute of Microelectronics, Tsinghu

University, Beijing 100084, China (e-mail: zhang.lei@tsinghua.edu.cn).

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