Int. J. Internet Protocol Technology, Vol. X, No. Y, 200x 1
Copyright © 20XX Inderscience Enterprises Ltd.
Markov parameters tuning prediction to improve
cache hit rate
Benbin Chen*
Department of Electronic Engineering,
Xiamen University,
Fujian 361005, China
Email: chenbenbin@163.com
*Corresponding author
Donghui Guo
Department of Electronic Engineering,
Xiamen University,
Fujian 361005, China
and
IC Design and IT Research Center of Fujian Province,
Fujian 361005, China
Email: dhguo@xmu.edu.cn
Abstract: Because the spatial and temporal locality of programme codes, compiler could use
heuristics and profile guided prediction to relocate the output of programme codes to reduce the
cache confliction. In this paper, for improving the average accessing time of memory subsystem
by raising the instructions cache hit rate, compiler-assisted Markov parameters tuning (MPT)
frequencies prediction techniques for codes relocation are proposed. Different with the traditional
schemes that provide the fixed heuristics branch probability (FHBP) to calculate nodes
frequencies (NF) for various kinds of programmes, the Markov-based heuristics algorithm
combining FHBP and parameters tuning techniques in MPT probability matrix is adopted for
improving programme NF prediction to take advantage of the probability matrix and model the
control flow graph (CFG) in function more precision. The MPT model was simulated to illustrate
the strengths of accurate expression of the programme. Compare with the actual execution results
of programme with profile coverage tests, the experimental result is better fit to validate its
feasibility.
Keywords: Markov; compiler assisted; cache hit rate; relocation; NF prediction.
Reference to this paper should be made as follows: Chen, B. and Guo, D. (xxxx) ‘Markov
parameters tuning prediction to improve cache hit rate’, Int. J. Internet Protocol Technology,
Vol. X, No. Y, pp.xxx–xxx.
Biographical notes: Benbin Chen is a PhD student in Electronic Engineering from Xiamen
University, Xiamen, China. He received his BE in Computer Science and Technology
Department, Changsha University of Science and Technology from 2000 to 2004 and MS in
Software School from Xiamen University from 2006 to 2008. He is currently working toward his
PhD degree. As a Senior System Analyst, his research interests include embedded system, and
compiler.
Donghui Guo received his PhD in Semiconductor Physics from Physical Department of Xiamen
University in 1994. He is now a Full Professor in Department of Electronic Engineering and the
Director of IC Design and IT Research Center, Xiamen University. His interesting areas include
artificial intelligence, telecommunication and IC design.
This paper is a revised and expanded version of a paper entitled ‘Compiler assisted instruction
relocation for performance improvement of cache hit rate and system reliability’ presented at the
Software Security and Reliability Companion Conference (SERE-C 2014), San Francisco,
California, USA, 30 June to 2 July 2014.
1 Introduction
The hierarchical memory subsystem becomes a performance
bottleneck (Pettis et al., 2004) because of the rapid
increasing processor speed. Cache was proposed to
eliminate the deep gap between the main memory and the
processor in the hierarchical memory model. However, the
small capacity and cache confliction limit the memory