异构可重构处理器在实时基带处理中的应用

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"Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing 2016" 是一本由Chenxin Zhang、Liang Liu和Viktor Öwall合著的书籍，探讨了异构可重构处理器在实时基带处理中的应用，从算法到架构的全方面解析。在这本书中，作者深入研究了如何利用异构可重构处理器来实现高效实时的基带处理。异构可重构处理器结合了不同类型的计算单元，如CPU、GPU、FPGA（现场可编程门阵列）和ASIC（专用集成电路），以适应各种复杂的计算任务。这种设计方法可以提供更高的性能和能效，特别是在处理通信系统中的实时基带信号时。实时基带处理是现代无线通信技术的核心部分，包括数字信号处理、信道编码和解码、同步以及调制解调等。这些任务需要高性能和低延迟，而传统的单片处理器可能无法满足这些要求。因此，采用异构可重构处理器能够根据任务需求动态调整硬件配置，从而优化性能和功耗。书中的内容可能涵盖了以下知识点： 1. **异构计算**：解释了异构计算的概念，即如何组合不同类型的处理器来提高整体性能和灵活性，以及如何管理这些不同的计算资源。 2. **可重构处理器**：详述了FPGA和其他可重构硬件的优势，如快速重新配置、低功耗和高度定制化能力。 3. **实时信号处理**：讨论了实时基带处理的挑战，包括时间约束、数据流管理和实时性保证。 4. **算法优化**：介绍了如何将基带处理算法优化以适应硬件，包括算法的并行化、流水线设计和数据压缩。 5. **体系结构设计**：探讨了如何设计和实现一个高效的异构处理器架构，以支持实时基带处理任务。 6. **案例研究**：可能包含实际的通信系统实例，展示如何应用这些理论到实际应用中。 7. **性能评估**：可能分析了不同处理器架构在基带处理任务中的性能差异，包括速度、功耗和资源利用率。通过这本书，读者可以了解到如何结合软件和硬件层面的创新，以实现更高效、更灵活的实时基带处理解决方案。这对于通信工程师、计算机科学家和电子工程师来说，是一本宝贵的参考资料，有助于他们在设计高性能通信系统时做出明智的决策。

Chapter 1

Introduction

This book discusses an interdisciplinary study in wireless communication and

Very-large-scale integration (VLSI) design, more speciﬁcally, implementation of

digital baseband processing using reconﬁgurable architectures. Development of

such kind of systems, sometimes referred to as baseband processors [15]or

Software-deﬁned radio (SDR) platforms [8], is an important and challenging

subject, especially for small-scale base stations (e.g., femtocells) and mobile

terminals that must provide reliable services under various operating scenarios with

low power consumption.

The importance of the subject is driven by two facts. First, there is a huge

demand for wireless communication in the world. The number of devices connected

to the Internet in one way or the other is expected to reach 50 billion by 2020

[3, 9]. In other words, every person on earth will have around six devices on

average. Second, the number of radio standards grows increasingly fast in order

to sufﬁce ever-growing user demands such as data rate. For example, compared to

the world’s ﬁrst hand-held device demonstrated in 1973, today’s fourth-generation

(4G) mobile terminals are able to process not only voice and text but also data

streaming with the speed of up to gigabit-per-second [7]; the coming 5G wireless

communication network will provide 1000-fold gain in capacity. Moreover, modern

wireless systems need to be backward compatible to support 2G Global system

for mobile communications (GSM) and 3G Universal mobile telecommunications

system (UMTS), as well as to support a range of different radio standards for

improving user experience. Examples of these standards are bluetooth, IEEE 802.11

series, Global positioning system (GPS), and Near ﬁeld communication (NFC). As

envisioned in [5], a single 4G mobile terminal needs to support more than 10 radio

standards with tens of operation modes in each standard [e.g., 63 for 3GPP Long

term evolution (LTE)]. Using traditional implementation strategies, equipping each

of these standards with an Application-speciﬁc integrated circuit (ASIC), becomes

antiquated and unaffordable with regard to area consumption and development time.

C. Zhang et al., Heterogeneous Reconﬁgurable Processors for Real-Time

Baseband Processing, DOI 10.1007/978-3-319-24004-6_1

2 1 Introduction

Besides, it is unlikely that a user will enable all of these standards at the same time

in a single terminal. Thus, there is a need for a ﬂexible hardware platform capable of

supporting operations among multiple standards and tasks and allocating resources

dynamically to sufﬁce current computational demands.

In addition to the multi-standard multi-task support, ﬂexibility is required to cope

with the rapid evolution of baseband processing algorithms and enable run-time

algorithm adaption to provide better Quality of service (QoS) and maintain robust,

reliable, and seamless connectivity. Furthermore, beneﬁting from the hardware

reconﬁgurability, such architectures have the potential to perform system updates

and bug-ﬁxes while the system is in operation. This feature will prolong product

life-time and ensure beneﬁts in terms of time-to-market [13, 15, 16]. Last but not

the least, from an algorithm development perspective, reconﬁgurable computing

provides a more software-centric programming approach. This allows hardware

platforms to be developed on-demand and potentially in the same language as

used for software development. Uniﬁed programming environment enhances pro-

ductivity by simplifying system integration and veriﬁcation. Besides its importance,

the target subject faces many design challenges in practical implementations, such

as requirements of high computational performance and low energy consumption.

Primary concerns for contemporary system designs are shifting from computational

performance to energy efﬁciency [2, 17]. This trend becomes more and more

prominent in wireless communication designs. For example, the transition from 3G

to 4G wireless communication systems demands 3 orders of magnitude increase in

computational complexity, whereas the total power budget remains approximately

constant in a single mobile terminal [14, 21]. Reconﬁgurable architectures, since its

invention in 1960 [10], promise to offer great hardware ﬂexibility and computational

performance. They allow run-time hardware reconﬁgurations to accelerate arbitrary

algorithms, and thus extend the application domain and versatility of the device.

However, due to huge routing overhead, they cannot match power and area efﬁ-

ciency of ASICs, in spite of their tremendous developments over the past decades.

As an example, ﬁne-grained interconnects in commercial Field-programmable gate

array (FPGA) consume over 75 % of the chip area [20], and cause 17–54 times

area overhead and 5.7–62 times more power consumption in comparison to ASICs

[12]. Moreover, bit-level function blocks of FPGAs incur additional area and

power penalties when implementing word-level computations. The area and power

overhead have restricted the usage of reconﬁgurable architectures in cost-sensitive

applications such as wireless communication in mobile terminals. To address these

overhead issues, new types of reconﬁgurable architectures with coarse-grained

function blocks have gained increasing attention in recent years in both academia

and industry [1, 4, 6, 11, 18, 19].

This book presents a coarse-grained dynamically reconﬁgurable cell array

architecture, which is designed and tailored with a primary focus on digital

baseband processing in wireless communication. By exploiting the computational

characteristics of the target application domain, the presented domain-speciﬁc cell

array architecture bridges the gap between ASICs and conventional reconﬁgurable

platforms. The ﬂexibility, performance, and hardware efﬁciency of the cell array are

demonstrated through case studies.

1.1 Scope of the Book 3

1.1 Scope of the Book

The goal of this book is to ﬁnd efﬁcient reconﬁgurable architectures that can provide

a balance among computational capability, ﬂexibility, and hardware efﬁciency.

The driving application for hardware developments and performance evaluations

is digital baseband processing in wireless communication. The target platform is

commercially deployed wireless communication equipment and devices, which

need to provide real-time performance with restricted budgets of physical size and

energy dissipation.

The central part of this book is the presentation of a dynamically reconﬁgurable

cell array architecture. Performance of the cell array is evaluated through two case

studies, which are conducted to address two following questions:

• Can the cell array be used for multi-standard and multi-task processing? Is the

control overhead affordable?

• Can the cell array meet real-time requirements when performing sophisticated

baseband processing tasks? Under such a use case, what is the area and energy

efﬁciency in comparison to ASICs and conventional reconﬁgurable architec-

tures?

Throughout the book and by conducting algorithm–architecture co-design, spe-

cial attention is paid to four distinct areas of the cell array design:

• System architecture design, including various processing elements, memory sub-

systems, Network-on-chip (NoC), and dynamic reconﬁguration.

• Design ﬂow of the cell array.

• Design trade-offs, including selection of processing elements and accelerators,

task partitioning between hardware and software as well as between processing

elements and memory sub-systems.

• Instruction set and function descriptor design for various processing elements

and memory sub-systems, respectively.

Digital baseband processing in wireless communication systems includes

many tasks such as Orthogonal frequency division multiplexing (OFDM) mod-

ulation/demodulation, Multiple-input multiple-output (MIMO) signal processing,

Forward error correction (FEC), interleaving, scrambling, etc. Among these, this

book focuses on four crucial blocks in a typical baseband processing chain at the

receiver, i.e., Digital front-end (DFE), channel estimation, channel pre-processing,

and symbol detection. However, the same design methodology is applicable for

other baseband processing blocks and applications.

4 1 Introduction

1.2 Outline

Chapters 2 and 3 serve to give an overview of the research ﬁeld. Chapter 2 discusses

reconﬁgurable architectures and various processing alternatives. Chapter 3 covers

typical digital baseband processing tasks in contemporary wireless communication

systems. These two introductory chapters are not intended to give detailed descrip-

tions on each of the subject. They are presented to give reference information on

terms and concepts used later in the book.

Chapter 4 introduces the coarse-grained dynamically reconﬁgurable cell array

architecture, including both system infrastructure and a hardware design ﬂow. Using

the cell array as a baseline architecture, Chaps. 5 and 6 present two case studies to

demonstrate the performance of the presented domain-speciﬁc reconﬁgurable cell

array. The two studies are conducted in accordance to the processing ﬂow of a

typical baseband processing chain at the receiver. In addition, the two case studies

manifest architectural evolution of the cell array, namely from scalar- to vector-

based architecture. Chapter 7 opens up discussion on reconﬁgurable architecture

design for next-generation wireless communication systems. Signal processing

operations in Massive MIMO and design challenges for reconﬁgurable platforms

are discussed.

1.2.1 Chapter 4: The Reconﬁgurable Cell Array

Conventional ﬁne-grained architectures, such as FPGAs, provide great ﬂexibility

by allowing bit-level manipulations in system designs. However, the ﬁne-grained

conﬁgurability results in long conﬁguration time and poor area and power efﬁciency,

and thus restricts the usage of such architectures in time-critical and area/power-

limited applications. To address these issues, recent work focuses on coarse-grained

architectures, aiming to provide a balance between ﬂexibility and hardware efﬁ-

ciency by adopting word-level data processing. In this chapter, a coarse-grained

dynamically reconﬁgurable cell array architecture is presented. The architecture

is constructed from an array of heterogeneous functional units communicating

via hierarchical network interconnects. The strength of the architecture lies in the

simpliﬁed data sharing achieved by decoupled processing and memory cells, the

substantial communication cost reduction obtained by a hierarchical network struc-

ture, and the fast context switching enabled by a unique run-time reconﬁguration

mechanism.

1.2 Outline 5

1.2.2 Chapter 5: Multi-Standard Digital Front-End Processing

This chapter aims at demonstrating the ﬂexibility of the reconﬁgurable cell array

architecture and evaluating the control overhead of hardware reconﬁgurations, in

terms of clock cycles and area consumption. For this purpose, the cell array is

conﬁgured to concurrently process multiple radio standards. Flexibility of the archi-

tecture is demonstrated by performing time synchronization and Carrier frequency

offset (CFO) estimation in a digital front-end receiver for multiple OFDM-based

standards. As a proof-of-concept, this book focuses on three contemporarily widely

used radio standards, 3GPP LTEs, IEEE 802.11n, and Digital video broadcasting

for handheld (DVB-H). The employed reconﬁgurable cell array, containing 2 2

resource cells, supports all three standards and is capable of processing two

concurrent data streams. Dynamic conﬁguration of the cell array enables run-time

switching between different standards and allows adoption of different algorithms

on the same platform. Thanks to the adopted fast conﬁguration scheme, context

switching between different operation scenarios requires at most 11 clock cycles.

1.2.3 Chapter 6: Multi-Task MIMO Signal Processing

This chapter aims at demonstrating the ﬂexibility and real-time processing capa-

bility of the cell array as well as evaluating the area and energy efﬁciency when

performing sophisticated baseband processing tasks.

Driven by the requirement of multi-dimensional computing in contemporary

wireless communication technologies, reconﬁgurable platforms have come to the

era of vector-based architectures. In this chapter, the reconﬁgurable cell array is

extended with extensive vector computing capabilities, aiming for high-throughput

baseband processing in MIMO-OFDM systems. Besides the heterogeneous and

hierarchical resource deployments, a vector-enhanced Single instruction multiple

data (SIMD) structure and various memory access schemes are employed. These

architectural enhancements are designed to sufﬁce stringent computational require-

ments while retaining high ﬂexibility and hardware efﬁciency. To demonstrate

its performance and ﬂexibility, three computationally intensive blocks, namely

channel estimation, channel pre-processing, and symbol detection, of a 4 4MIMO

processing chain in a 20 MHz 64-QAM 3GPP Long term evolution-advanced (LTE-

A) downlink are mapped and processed in real-time.

1.2.4 Chapter 7: Future Multi-User MIMO Systems

This chapter looks ahead into advanced multi-user Massive MIMO technology

for 5G wireless communication systems and opens up discussion for its baseband

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