"2022版JESD78F IC Latch-Up测试标准详解及下载"

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The JESD78F 2022 IC LATCH-UP TEST.pdf is a standard document that specifies the testing procedures and requirements for Integrated Circuit (IC) latch-up testing. This document, a revision of the JESD78E from April 2016, was released in January 2022 and downloaded by user cdm_lj@163.com on June 13, 2022, at 1:20 am PDT. The document begins with a notice from JEDEC, stating that its standards and publications are prepared, reviewed, and approved through the JEDEC Board of Directors and legal counsel to serve the public interest by eliminating misunderstandings and conflicts. This emphasizes the importance and credibility of the standards outlined in the document. The content of the JESD78F 2022 IC LATCH-UP TEST.pdf includes specific guidelines and requirements for IC latch-up testing. It covers various aspects such as testing procedures, test conditions, test setup, and test results interpretation. Additionally, the document may also provide information on the types of ICs that are subject to this testing requirement, as well as the potential impact of latch-up on IC functionality and reliability. Overall, the JESD78F 2022 IC LATCH-UP TEST.pdf serves as a comprehensive guide for manufacturers, testing labs, and other relevant parties in the semiconductor industry to ensure the quality, reliability, and performance of IC products. Compliance with this standard is essential for meeting industry requirements and delivering trustworthy products to the market. It also demonstrates the industry's commitment to upholding high standards of quality and reliability in IC manufacturing and testing processes.

JEDEC Standard No. 78F

Page 4

2 Terms and Definitions (cont’d)

“no connect” pin: A pin that has no internal electrical connection to the die.

NOTE All “no connect” pins are to be left in an open (floating) state and should not be stressed during latch-up

testing.

nominal I

supply

nom

): The measured dc supply current for each V

supply

pin (or pin group) with the DUT

biased at the maximum operating conditions.

output pins: A subgroup of signal pins that are not configured to receive an external signal during latch-up

testing because they drive out a signal or a voltage level.

NOTE 1 Output pins, though left in an open (floating) state during testing of other pin types, should be latch-up

tested.

NOTE 2 Output pins are typically in a low-impedance state.

NOTE 3 This definition reflects the usage within this latch-up test specification. Datasheets may use a different

definition of output pins focusing on actual system applications (see section 5.4.1.)

power supply: A component in the test system that supplies voltage and current to the DUT.

preconditioned pin: A device pin that has been placed in a defined state or condition by applying static or

dynamic control signals to the DUT or biasing the appropriate steady state control pin(s) in order to put the

device into a known, controlled and stable state.

preconditioning vectors: a series of commands sent to an integrated circuit instructing the circuit to perform

a specified series of functions or place it into a known state.

pre-stress & post-stress current (I

psPRE

psPOST

): The pulse supply current corresponding to the Signal Pin

Test or Supply Test before (pre-stress) & after (post-stress) pulse application.

NOTE 1 I

psPRE

psPOST

can either be a forced value or the limit value depending on the mode of the source (I-Test or

E-Test).

NOTE 2 It is also known as parking current in some commercial systems.

pre-stress & post-stress voltage (V

psPRE

& V

psPOST

): The pulse supply voltage corresponding to the Signal

Pin Test or Supply Test before (pre-stress) & after (post-stress) pulse application. It is not dependent on

polarity.

NOTE 1 V

psPRE

psPOST

can either be a forced value or the limit value depending on the mode of the source (I-Test

or E-Test).

NOTE 2 V

psPRE

psPOST

are typically either V

maxOP

or V

minOP

for these systems.

NOTE 3 It is also known as parking voltage in some commercial systems.

PUT: Pin Under Test

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JEDEC

JEDEC Standard No. 78 F

Page 5

2 Terms and Definitions (cont’d)

signal pins: Device pins that carry an electrical signal (information) during stable operation of the device

and are not used as supply pins.

Signal Pin Test: A test that injects positive and negative current pulses to the pin under test (PUT) by either

injecting a current pulse (I-Test) with a voltage limit or injecting a voltage pulse (E-Test) with a current limit.

steady state control pins: Pins used to place the DUT in the desired configuration (IO configuration pins,

reset, power good/OK, enable, other control pins) whose logic or bias state remains constant for the duration

of the test. (See Section 5.4.1)

NOTE Steady state control pins, though remaining in a constant state, may still be latch-up tested with a stress pulse

polarity that does not alter their logic state.

Supply Test (previously V

supply

overvoltage test): A latch-up test that supplies overvoltage pulses to the

supply pin (or pin group) under test.

temperature, maximum operating junction (T

jmax

): The maximum junction temperature of a device to

operate within its specifications, as listed in its data sheet and to avoid damage (latent or otherwise). It is

frequently specified by device manufacturers for a specific device and/or technology.

temperature, junction (T

): The temperature of a semiconductor junction in a device.

temperature, ambient (T

): The local air temperature surrounding the device, in an environment controlled

only by natural air convection and not materially affected by reflective and radiant surfaces.

temperature, case (T

): The temperature measured or calculated on the case surface of a device. (As per

JESD88F)

NOTE See 3.2 and/or Annex B for further information on measuring/calculating case temperature using ambient or

junction.

timing-related input pin: A pin such as clock crystal oscillator, charge pump circuit, etc., required to place

the DUT in a stable operating mode. Required timing signals may be applied by the latch-up tester, external

equipment, and/or external components as appropriate.

test condition: The test temperature, supply voltage, current limits, voltage limits, clock frequency, input

bias voltages and preconditioning vectors applied to the DUT during the latch-up test.

trigger duration: The duration of an applied pulse from the trigger source.

trigger pulse: The positive or negative current pulse (Signal Pin Test) or voltage pulse (Supply Test or

E-Test) applied to any pin under test for latch-up sensitivity.

tri-state (also known as three-state): Cells or macros whose outputs can be placed in a high-impedance state

and can also generate low-impedance V

maxOP

and V

minOP

levels. (Ref JESD12-4, 4/87)

limit

: The value of voltage used to limit the actual voltage, and thereby restricts the forced current into and

out of a signal pin during latch-up stress.

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JEDEC

JEDEC Standard No. 78 F

Page 7

3 Latch-up Characterization

A component’s susceptibility to a latch-up event is characterized by its response to a stress when either

current is injected into a signal pin or when a supply overvoltage occurs operating within the temperature

range of the component’s specified operating junction temperature. This section describes the Immunity

Levels (A and B) and the temperature classification (II and I) for latch-up characterization.

3.1 Latch-up immunity

Product latch-up immunity is characterized by the forced current or voltage value at the signal pin and

overvoltage value on the supplies that does not result in latch-up as defined in this test standard. Table 1

defines Immunity Levels A and B at specified ranges for injected current and applied voltage stress levels.

Table 1 --- Latch-up immunity levels

Immunity

Level

Test

Absolute Magnitude of Injected Trigger Current

Absolute Magnitude of Applied Trigger Voltage

Positive Signal Pin Test

(1)

≥ 100 mA

The actual injected current may be less than 100 mA,

if pin voltage preset limits are reached

Negative Signal Pin Test

(1)

Supply Test

1.5 × V

maxSUP

or MSV, whichever is less

The actual applied voltage may be less than 1.5 × V

maxSUP

or MSV, if supply current limits are reached

If Immunity Level A cannot be achieved

(1) In the Signal Pin Test, current injection is achieved either by current forcing with voltage

compliance limit (I-Test) or by applying voltage with current compliance limit (E-Test).

The actual current injected into the signal pin during the Signal Pin Test may be limited by the signal pin

design or due to the test methods described in Table 2 for the preset conditions that limit the signal pin

voltage during the current injection. Likewise, the actual applied voltage during the Supply Test may be

limited by the preset current limit into the supply. If latch-up does not occur in such a condition, then this

constitutes a passing test with Immunity Level A. Otherwise, it is classified with Immunity Level B.

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JEDEC

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